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| description the 3807 group is a 8-bit microcomputer based on the 740 family core technology. the 3807 group has two serial i/os, an a-d converter, a d-a converter, a real time output port function, a watchdog timer, and an analog comparator, which are available for a system controller which controls motors of office equipment and household appliances. the various microcomputers in the 3807 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3807 group, refer to the section on group expansion. ? serial i/o1 (uart or clock-synchronized) .................... 8-bit 5 1 ? serial i/o2 (clock-synchronized) ................................... 8-bit 5 1 ? a-d converter ................................................ 8-bit 5 13 channels ? d-a converter .................................................. 8-bit 5 4 channels ? watchdog timer ............................................................ 16-bit 5 1 ? analog comparator ........................................................ 1 channel ? 2 clock generating circuit main clock (x in Cx out ) .......................... internal feedback resistor sub-clock (x cin Cx cout ) .......... without internal feedback resistor ( connect to external ceramic resonator or quartz-crystal oscillator ) ? power source voltage in high-speed mode ................................................... 4.0 to 5.5 v (at 8 mhz oscillation frequency and high-speed selected) in middle-speed mode ................................................ 2.7 to 5.5 v (at 8 mhz oscillation frequency and middle-speed selected) in low-speed mode ..................................................... 2.7 to 5.5 v (at 32 khz oscillation frequency and low-speed selected) ? power dissipation in high-speed mode ......................................................... 34 m w (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................. 60 m w (at 32 khz oscillation frequency, at 3 v power source voltage) ? memory expansion .......................................................... possible ? operating temperature range ................................... C20 to 85 c application lbp engine control, ppc, fax, office equipment, household appli- ances, consumer electronics, etc. features ? basic machine-language instructions ....................................... 71 ? the minimum instruction execution time ............................ 0.5 m s (at 8 mhz oscillation frequency) ? memory size ................................................................................. rom ................................................ 8 to 60 k bytes ram ............................................ 384 to 2048 bytes ? programmable input/output ports ............................................. 68 ? software pull-up resistors (ports p0 to p2) .............................. 24 ? input ports (ports p6 3 and p6 4 ) ................................................. 2 ? interrupts .................................................. 20 sources, 16 vectors ? timers x, y .................................................................. 16-bit 5 2 ? timers a, b (for real time output port function) ............ 16-bit 5 2 ? timers 1C3 ..................................................................... 8-bit 5 3 fig. 1. pin configuration of m38073m4-xxxfp package type : 80p6n-a 80-pin plastic-molded qfp pin configuration (top view) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p3 0 /rtp 6 p3 1 /rtp 7 p3 4 /ck out / f p3 5 /sync p0 0 /ad 0 p0 3 /ad 3 p0 4 /ad 4 p0 5 /ad 5 p0 6 /ad 6 p0 7 /ad 7 p1 1 /ad 9 p1 2 /ad 10 p1 3 /ad 11 p1 4 /ad 12 p1 5 /ad 13 p1 6 /ad 14 p1 7 /ad 15 p6 2 /an 7 p6 1 /an 6 p6 0 /an 5 p7 7 /an 4 m38073m4-xxxfp p7 6 /an 3 p7 5 /an 2 p7 4 /an 1 p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p5 7 /da 2 p5 0 /t out p4 6 /s clk1 p4 5 /t x d p4 4 /r x d p4 3 /int 1 p6 3 /cmp in /an 8 p6 4 /cmp ref /an 9 p6 5 /dav ref /an 10 av ss adv ref v cc p8 0 /da 3 /an 11 p8 1 /da 4 /an 12 p8 2 /rtp 0 p8 3 /rtp 1 p8 4 /rtp 2 p8 5 /rtp 3 p8 6 /rtp 4 p8 7 /rtp 5 p4 2 /int 0 cnv ss x in x out v ss p2 7 /db 7 p2 6 /db 6 p2 5 /db 5 p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 1 /db 1 p2 0 /db 0 reset p7 3 /s rdy2 /adt/an 0 p5 1 /s cmp2 /int 2 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 4 p5 2 /int 3 p5 6 /da 1 p1 0 /ad 8 p0 1 /ad 1 p0 2 /ad 2 p4 7 /s rdy1 p3 2 /onw p3 3 /reset out p3 6 /wr p3 7 /rd p4 0 /x cout p4 1 /x cin cmp out cmpv cc mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer
2 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer fig. 2. functional block diagram functional block diagram (package : 80p6n) functional block cntr 0 cntr 1 adv ref av ss int 4 int 2 int 1 int 0, t out rtp 5 rtp 0 int 4 r a m r o m c p u a x y s pc h pc l ps ss v 32 reset 27 cc v 73 26 cnv ss p0(8) 49 50 51 52 53 54 55 56 p1(8) 41 43 45 47 42 44 46 48 p2(8) 33 35 37 39 34 36 38 40 p3(8) 57 59 61 63 58 60 62 64 p4(8) 20 22 24 28 21 23 25 29 p5(8) 12 14 16 18 13 15 17 19 p7(8) 4 6 8 10 57 9 11 p8(8) 65 67 69 71 66 68 70 72 p6(8) 76 78 2 77 1 3 74 75 rtp x in 30 out x 31 si/o1(8) si/o2(8) d-a (8) d-a (8) d-a (8) d-a (8) 80 79 reset input clock generating circuit main clock input main clock output a-d converter converter 2 converter 1 timer y (16) timer x (16) timer 1 (8) timer 3 (8) timer 2 (8) i/o port p 4 i/o port p 0 i/o port p 1 i/o port p 2 i/o port p 3 i/o port p 5 i/o port p 7 i/o port p 8 i/o port p 6 (8) int 0 t out rtp 5 rtp 0 converter 4 x cin x cout dav ref int 1 timer b (16) timer a (16) x cin x cout analog comparator cmpv cc cmp out cmp ref cmp in cmp ref cmp in s cmp2 s cmp2 sub clock input sub clock output converter 3 3 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3807 group pin description pin name function v cc , v ss power source ? apply voltage of 2.7C5.5 v to v cc , and 0 v to v ss . cmpv cc analog comparator ? power source input pin for an analog comparator power source cnv ss cnv ss ? this pin controls the operation mode of the chip. ? normally connected to v ss . ? if this pin is connected to v cc , the internal rom is inhibited and external memory is accessed. adv ref analog reference ? reference voltage input pin for a-d converter. voltage av ss analog power ? analog power source input pin for a-d and d-a converter and an analog comparator source ? connect to v ss . cmp out analog comparator ? output pin for an analog comparator output ______ reset reset input ? reset input pin for active l x in clock input ? input and output signals for the internal clock generating circuit. ? connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. x out clock output ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ? the clock is used as the oscillating source of system clock. p0 0 Cp0 7 i/o port p0 ? 8-bit cmos i/o port p1 0 Cp1 7 i/o port p1 ? i/o direction register allows each pin to be individually programmed as either input or output. p2 0 Cp2 7 i/o port p2 ? at reset this port is set to input mode. ? in modes other than single-chip, these pins are used as address, data bus i/o pins. ? cmos compatible input level ? cmos 3-state output structure ? port p2 can be switched cmos or ttl input level. p3 0 /rtp 6 , i/o port p3 ? 8-bit cmos i/o port ? real time port function p3 1 /rtp 7 ? i/o direction register allows each pin to be individually programmed as either input or output. pins p3 4 /ck out , ? at reset this port is set to input mode. ? clock output function pin p3 2 , p3 3 , ? in modes other than single-chip, these pins are used as control bus i/o pins. p3 5 Cp3 7 ? cmos compatible input level ? cmos 3-state output structure ? port p3 2 can be switched cmos or ttl input level. p4 0 /x cout , i/o port p4 ? 8-bit cmos i/o port with the same function as port p0 ? sub-clock generating i/o p4 1 /x cin ? cmos compatible input level pins (connect a resonator) p4 2 /int 0 , ? cmos 3-state output structures ? interrupt input pins p4 3 /int 1 ? timer x, timer y function pins (int 0 , int 1 ) p4 4 /r x d, ? serial i/o1 function pins p4 5 /t x d, p4 6 /s clk1 , p4 7 /s rdy1 p5 0 /t out i/o port p5 ? 8-bit cmos i/o port with the same function as port p0 ? timer 2 output pin p5 1 /s cmp2 / ? cmos compatible input level ? interrupt input pin int 2 ? cmos 3-state output structure ? serial i/o2 function pin p5 2 /int 3 , ? interrupt input pin p5 3 /int 4 ? real time port function pin(int 4 ) p5 4 /cntr 0 , ? timer x, timer y function pins p5 5 /cntr 1 p5 6 /da 1 , ? d-a conversion output p5 7 /da 2 pins function except a port function table. 1. pin description (1) 4 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer table. 2. pin description (2) pin name function p6 0 /an 5 C i/o port p6 ? 3-bit cmos i/o port with the same function as port p0 ? a-d conversion output p6 2 /an 7 ? cmos compatible input level pins ? cmos 3-state output structure p6 3 /cmp in / input port p6 ? 2-bit cmos input port ? analog comparator input pin an 8 ? cmos compatible input level ? a-d conversion input pin p6 4 / cmp ref / ? reference voltage input pin an 9 for analog comparator ? a-d conversion input pin p6 5 / dav ref / i/o port p6 ? 1-bit cmos i/o port with the same function as port p0 ? d-a conversion power an 10 ? cmos compatible input level source input pin ? cmos 3-state output structure ? a-d conversion input pin p7 0 /s in2 , i/o port p7 ? 8-bit cmos i/o port with the same function as port p0 ? serial i/o2 function pins p7 1 /s out2 , ? cmos compatible input level p7 2 /s clk2 ? cmos 3-state output structures p7 3 /s rdy2 / ? serial i/o2 function pin adt/an 0 ? a-d conversion input pin ? a-d trigger input pin p7 4 /an 1 C ? a-d conversion input pin p7 7 /an 4 p8 0 /da 3 / i/o port p8 ? 8-bit cmos i/o port with the same function as port p0 ? d-a conversion output an 11, ? cmos compatible input level pin p8 1 /da 4 / ? cmos 3-state output structures ? a-d conversion input pin an 12, p8 2 /rtp 0 C ? realtime port function p8 7 /rtp 5 pins function except a port function 5 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3807 group part numbering fig. 3. part numbering m3807 3 m 4 - xxx fp product package type fp : 80p6n-a package fs : 80d0 package rom number omitted in some types. rom/prom size 1 2 3 4 5 6 7 8 9 a b c d e f : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m e : mask rom version : eprom or one time prom version ram size 0 1 2 3 4 5 6 7 8 9 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes 6 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer 48k 32k 28k 24k 20k 16k 12k 8k 384 512 640 768 896 1024 60k 1152 1280 1408 1536 external rom 2048 3072 4032 mass product m38079ef under development rom size (byte) ram size (byte) being planned m38078mc mass product m38073e4 being planned m38077m8 m38078s being planned m38073m4 fig. 4. memory expansion plan currently supported products are listed below. table 3. list of supported products (p) rom size (bytes) product ram size (bytes) package remarks rom size for user () m38073m4-xxxfp mask rom version m38073e4-xxxfp 16384 512 80p6n-a one time prom version m38073e4fp (16254) one time prom version (blank) m38073e4fs 80d0 eprom version note : products under development or planning : the development schedule and specifications may be revised without notice. as of may 1996 group expansion mitsubishi plans to expand the 3807 group as follows: memory type support for mask rom, one time prom and eprom versions. memory size rom/prom size .................................................... 8k to 60k bytes ram size ............................................................. 384 to 2048 bytes package 80p6n-a ..................................... 0.8 mm-pitch plastic molded qfp 80d0 ........................ 0.8 mm-pitch ceramic lcc (eprom version) 7 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer functional description central processing unit (cpu) the 3807 group uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instruc- tions or the series 740 8 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer memory special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the reset is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. fig. 6. memory map diagram 0100 16 0000 16 0040 16 0840 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 1536 2048 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom reserved area sfr area not used interrupt vector area rom area reserved rom area (128 byte) zero page special page ram area ram capacity (byte) address xxxx 16 rom capacity (byte) address yyyy 16 reserved rom area address zzzz 16 9 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer fig. 7. memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 serial i/o2 register (sio2) port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) timer xy control register (txycon) port p2p3 control register (p2p3c) pull-up control register (pull) watchdog timer control register (wdtcon) transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) serial i/o2 control register 1 (sio2con1) serial i/o2 control register 2 (sio2con2) real time port control register 3 (rtpcon3) interrupt control register 2(icon2) a-d conversion register (ad) timer x (low-order) (txl) timer x (high-order) (txh) timer y (low-order) (tyl) timer y (high-order) (tyh) timer 1 (t1) timer 2 (t2) timer 3 (t3) timer x mode register (txm) timer y mode register (tym) timer 123 mode register (t123m) real time port register (rtp) real time port control register 0 (rtpcon0) real time port control register 1 (rtpcon1) real time port control register 2 (rtpcon2) timer a (low-order) (tal) timer a (high-order) (tah) timer b (low-order) (tbl) timer b (high-order) (tbh) d-a control register (dacon) a-d control register (adcon) d-a1 conversion register (da1) d-a2 conversion register (da2) d-a3 conversion register (da3) d-a4 conversion register (da4) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) 10 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer i/o ports [direction registers] pid the 3807 group has 68 programmable i/o pins arranged in nine indi- vidual i/o ports (p0p5, p6 0 p6 2 , p6 5 and p7p8). the i/o ports have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. when "0" is written to the bit corresponding to a pin, that pin becomes an input pin. when "1" is written to that pin, that pin becomes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input (the bit corre- sponding to that pin must be set to "0") are floating and the value of that pin can be written to. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. [pull-up control register] pull ports p0, p1 and p2 have built-in programmable pull-up resistors. the pull-up resistors are valid only in the case that the each control bit is set to "1" and the corresponding port direction registers are set to input mode. (1) cmos/ttl input level selection either cmos input level or ttl input level can be selected as an input level for ports p2 0 to p2 7 and p3 2 . the input level is selected by p2p3 2 input level selection bit (b7) of the port p2p3 control register (address 0015 16 ). when the bit is set to "0", cmos input level is selected. when the bit is set to "1", the ttl input level is selected. after this bit is re-set, its initial value depends on the state of the cnvss pin. when the cnvss pin is connected to vss, the initial value becomes "0". when the cnvss pin is connected to vcc, the initial value becomes "1". (2) notes on stp instruction execution make sure that the input level at each pin is either 0v or to vcc during execution of the stp instruction. when an input level is at an inter- mediate potential, a current will flow from vcc to vss through the input-stage gate. fig. 8. structure of port p2p3 control register fig. 9. structure of pull-up control register b7 port p2p3 control register (p2p3c : address 0015 16 ) p3 4 clock output control bit 0: i/o port 1: clock output output clock frequency selection bit 000: f 001: f(x cin ) 010: ??fixed output 011: ??fixed output 100: f(x in ) (f(x cin ) in low-speed mode) 101: f(x in )/2 (f(x cin )/2 in low-speed mode) 110: f(x in )/4 (f(x cin )/4 in low-speed mode) 111: f(x in )/16 (f(x cin )/16 in low-speed mode) not used (return "0" when read) p2 p3 2 input level selection bit 0: cmos level input 1: ttl level input b0 0: no pull-up 1: pull-up pull-up control register (pull : address 0016 16 ) p0 0 ?0 3 pull-up control bit p0 4 ,p0 5 pull-up control bit p0 6 pull-up control bit p0 7 pull-up control bit p1 0 ?1 3 pull-up control bit p1 4 ?1 7 pull-up control bit p2 0 ?2 3 pull-up control bit p2 4 ?2 7 pull-up control bit b7 b0 11 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer table. 4. list of i/o port functions (1) pin name input/output i/o format non-port function related sfrs ref.no. p0 0 Cp0 7 port p0 input/output, cmos compatible input level address low-order byte output cpu mode register (1) p1 0 Cp1 7 port p1 individual bits cmos 3-state output address high-order byte output pull-up control register p2 0 Cp2 7 port p2 cmos/ttl input level data bus i/o cpu mode register cmos 3-state output pull-up control register port p2p3 control register p3 0 /rtp 6 , port p3 cmos compatible input level real time port output cpu mode register (2) p3 1 /rtp 7 cmos 3-state output real time port control register p3 2 cmos/ttl input level control signal input cpu mode register (3) cmos 3-state output port p2p3 control register p3 3 cmos compatible input level control signal output cpu mode register cmos 3-state output p3 4 /ck out clock output, f output cpu mode register (4) port p2p3 control register p3 5 Cp3 7 control signal i/o cpu mode register (3) p4 0 /x cout , port p4 sub-clock generating circuit cpu mode register (5) p4 1 /x cin (6) p4 2 /int 0 , external interrupt input interrupt edge selection register (7) p4 3 /int 1 timer x, timer y function input p4 4 /r x d, serial i/o1 function i/o serial i/o1 control register (8) p4 5 /t x d, uart control register (9) p4 6 /s clk1 , (10) p4 7 /s rdy1 (11) p5 0 /t out port p5 timer 2 output timer 123 mode register (12) p5 1 /s cmp2 / external interrupt input interrupt edge selection register (22) int 2 serial i/o2 function i/o serial i/o2 control register p5 2 /int 3 , external interrupt input interrupt edge selection register (7) p5 3 /int 4 real time port trigger input (int 4 ) p5 4 /cntr 0 timer x, timer y function i/o timer x mode register (13) p5 5 /cntr 1 timer y mode register p5 6 /da 1 , d-a conversion output d-a control register (14) p5 7 /da 2 p6 0 /an 5 port p6 a-d conversion input a-d control register (15) p6 2 /an 7 p6 3 /cmp in / input cmos compatible input level analog comparator input pin a-d control register (16) an 8 a-d conversion input p6 4 / cmp ref / analog comparator reference an 9 voltage input pin a-d conversion input p6 5 / dav ref / input/output, cmos compatible input level d-a converter power source a-d control register (17) an 10 individual bits cmos 3-state output input a-d conversion input p7 0 /s in2 , port p7 serial i/o2 function i/o serial i/o2 control register (18) p7 1 /s out2, (19) p7 2 /s clk2 (20) p7 3 /s rdy2 / serial i/o2 function i/o serial i/o2 control register (21) adt/an 0 a-d trigger input a-d control register a-d conversion input p7 4 /an 1 a-d conversion input a-d control register (15) p7 7 /an 4 12 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer table. 5. list of i/o port functions (2) pin name input/output i/o format non-port function related sfrs ref.no. p8 0 /da 3 / port p8 input/output, cmos compatible input level d-a conversion output d-a control register (14) an 11 individual bits cmos 3-state output a-d conversion input a-d control register p8 1 /da 4 / an 12 p8 2 /rtp 0 real time port output real time port control (23) p8 7 /rtp 5 register note1 : for details of the functions of ports p0 to p3 in modes other than single-chip mode, and how to use double-function ports as f unction i/o ports, refer to the applicable sections. 2 : make sure that the input level at each pin is either 0 v or vcc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from vcc to vss through the input-stage gate. 13 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer fig. 10. port block diagram (1) (8) port p4 4 direction register data bus serial i/o1 enable bit receive enable bit port latch serial i/o1 input (3) ports p3 2 ,p3 3 ,p3 5 ?3 7 direction register data bus port latch (6) port p4 1 direction register data bus port x c switch bit port latch sub-clock oscillating circuit input (5) port p4 0 direction register data bus port x c switch bit port latch oscillator port p4 1 port x c switch bit (7) ports p4 2 ,p4 3 ,p5 2 ,p5 3 data bus direction register port latch interrupt input timer x input (p4 2 ) timer y input (p4 3 ) rtp trigger input (p5 3 ) except p5 2 *1 either cmos input level or ttl input level can be selected as an input level for ports p2 0 to p2 7 and p3 2 by p2?3 2 input level selection bit. *1 (1) ports p0?2 direction register data bus port latch pull-up control *1 (2) ports p3 0 ,p3 1 data bus port latch data for real time port direction register real time port output selection bit (4) port p3 4 data bus port latch clock output direction register clock output control 14 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer (9) port p4 5 data bus serial i/o1 enable bit transmit enable bit serial i/o1 output p4 5 /t x d p-channel output disable bit port latch (11) port p4 7 data bus serial i/o1 ready output port latch serial i/o1 mode selection bit serial i/o1 enable bit s rdy1 output enable bit (10) port p4 6 serial i/o1 synchronous clock selection bit serial i/o1 enable bit data bus serial i/o1 clock output serial i/o1 external clock input serial i/o1mode selection bit serial i/o1enable bit port latch direction register (13) ports p5 4 ,p5 5 port latch data bus timer output cntr 0 , cntr 1 interrupt input "001" "100" "101" "110" timer x, timer y operating mode bits (14) ports p5 6 ,p5 7 ,p8 0 ,p8 1 d-a conversion output data bus port latch da 1 output enable bit (p5 6 ) da 2 output enable bit (p5 7 ) da 3 output enable bit (p8 0 ) da 4 output enable bit (p8 1 ) a-d conversion input analog input pin selection bit except p5 6 ,p5 7 (15) ports p6 0 ?6 2, p7 4 ?7 7 analog input pin selection bit a-d conversion input data bus port latch (16) ports p6 3, p6 4 analog input pin selection bit a-d conversion input data bus analog comparator input (12) port p5 0 port latch data bus t out output control bit timer 2 output direction register direction register direction register direction register direction register direction register fig. 11. port block diagram (2) 15 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer fig. 12. port block diagram (3) (18) port p7 0 serial i/o2 input data bus direction register port latch (19) port p7 1 data bus port latch direction register serial i/o2 transmit completion signal serial i/o2 port selection bit serial i/o2 clock output p7 1 /s out2 p-channel output disable bit (17) port p6 5 data bus direction register port latch d-a conversion power source input a-d conversion input analog input pin selection bit (23) ports p8 2 ?8 7 data bus port latch data for real time port direction register real time port output selection bit (22) port p5 1 data bus serial i/o2 i/o comparison signal output port latch direction register interrrupt input serial i/o2 i/o comparison signal control bit (20) port p7 2 data bus port latch direction register serial i/o2 synchronous clock selection bit serial i/o2 port selection bit serial i/o2 clock output serial i/o2 external clock input p7 2 /s clk2 p-channel output disable bit (21) port p7 3 data bus port latch direction register serial i/o2 ready output s rdy2 output enable bit a-d conversion input a-d trigger interrupt input analog input pin selection bit ad external trigger valid bit 16 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer interrupts interrupts occur by twenty sources: eight external, eleven internal, and one software. (1) interrupt control each interrupt except the brk instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. an interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". interrupt enable bits can be set or cleared by software. inter- rupt request bits can be cleared by software, but cannot be set by software. the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt and reset. if several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. (2) interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack 3. concurrently with the push operation, the interrupt jump desti- nation address is read from the vector table into the program counter. 4. the interrupt disable flag is set and the corresponding inter- rupt request bit is cleared. n notes on use when the active edge of an external interrupt (int 0 int 4 , cntr 0 or cntr 1 ) is set or the timer /int interrupt source and the adt/ a-d conversion interrupt source are changed, the corresponding interrupt request bit may also be set. therefore, please take follow- ing sequence: (1) disable the external interrupt which is selected. (2) change the active edge in interrupt edge selection register (in case of cntr 0 : timer x mode register ; in case of cntr 1 : timer y mode register). (3) clear the set interrupt request bit to "0." (4) enable the external interrupt which is selected. 17 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer table. 6. interrupt vector addresses and priority note1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) interrupt request interrupt source priority remarks high low generating conditions reset (note 2) 1 fffd 16 fffc 16 at reset non-maskable int 0 2 fffb 16 fffa 16 at detection of either rising or falling edge of external interrupt int 0 input (active edge selectable) int 1 3 fff9 16 fff8 16 at detection of either rising or falling edge of external interrupt int 1 input (active edge selectable) serial i/o1 4 fff7 16 fff6 16 at completion of serial i/o1 data receive valid when serial i/o1 is selected receive serial i/o1 5 fff5 16 fff4 16 at completion of serial i/o1 data transmit valid when serial i/o1 is selected transmit shift or when transmit buffer is empty timer x 6 fff3 16 fff2 16 at timer x underflow timer y 7 fff1 16 fff0 16 at timer y underflow int 3 8 ffef 16 ffee 16 at detection of either rising or falling edge of external interrupt int 3 input (active edge selectable) valid when int 3 interrupt is selected timer 2 at timer 2 underflow valid when timer 2 interrupt is selected int 4 9 ffed 16 ffec 16 at detection of either rising or falling edge of external interrupt int 4 input (active edge selectable) valid when int 4 interrupt is selected timer 3 at timer 3 underflow valid when timer 3 interrupt is selected cntr 0 10 ffeb 16 ffea 16 at detection of either rising or falling edge of external interrupt cntr 0 input (active edge selectable) cntr 1 11 ffe9 16 ffe8 16 at detection of either rising or falling edge of external interrupt cntr 1 input (active edge selectable) serial i/o2 12 ffe7 16 ffe6 16 at completion of serial i/o2 data transmit valid when serial i/o2 is selected and receive int 2 13 ffe5 16 ffe4 16 at detection of either rising or falling edge of external interrupt int 2 input (active edge selectable) valid when int 2 interrupt is selected timer 1 at timer 1 underflow valid when timer 1 interrupt is selected timer a 14 ffe3 16 ffe2 16 at timer a underflow timer b 15 ffe1 16 ffe0 16 at timer b underflow a-d conversion 16 ffdf 16 ffde 16 at completion of a-d conversion valid when a-d interrupt is selected adt at falling edge of adt input external interrupt(valid at falling) valid when adt interrupt is selected and when a-d external trigger is selected. brk instruction 17 ffdd 16 ffdc 16 at brk instruction execution non-maskable software interrupt 18 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer fig. 14. structure of interrupt-related registers b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 interrupt edge selection bit int 1 interrupt edge selection bit int 2 interrupt edge selection bit int 3 interrupt edge selection bit int 4 interrupt edge selection bit timer 1/int 2 interrupt source bit timer 2/int 3 interrupt source bit timer 3/int 4 interrupt source bit (intedge : address 003a 16 ) 0 : falling edge active 1 : rising edge active interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 2/int 3 interrupt request bit timer 3/int 4 interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 2/int 3 interrupt enable bit timer 3/int 4 interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 cntr 0 interrupt request bit cntr 1 interrupt request bit serial i/o2 interrupt request bit timer 1/int 2 interrupt request bit timer a interrupt request bit timer b interrupt request bit adt/ad conversion interrupt request bit not used (returns "0" when read) (ireq2 : address 003d 16 ) interrupt control register 2 cntr 0 interrupt enable bit cntr 1 interrupt enable bit serial i/o2 interrupt enable bit timer 1/int 2 interrupt enable bit timer a interrupt enable bit timer b interrupt enable bit adt/ad conversion interrupt enable bit not used (returns "0" when read) (do not write "1" to this bit) 0 : interrupt disabled 1 : interrupt enabled (icon2 : address 003f 16 ) 0 : int interrupt selected 1 : timer interrupt selected interrupt disable flag i interrupt request interrupt request bit interrupt enable bit brk instruction reset fig. 13. interrupt control 19 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer timers the 3807 group has seven timers : four 16-bit timers (timer x, timer y, timer a, and timer b) and three 8-bit timers (timer 1, timer 2, and timer 3). all timers are down-counters. when the timer reaches either "00 16 " or "0000 16 ", an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. when a timer underflows, the interrupt request bit corresponding to that timer is set to "1." read and write operation on 16-bit timer must be performed for both high- and low-order bytes. when reading a 16-bit timer, read from the high-order byte first. when writing to 16-bit timer, write to the low- order byte first. the 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. timers a and b are real time output port timers. for details, refer to the section "real time output port". l timer x, timer y timer x and y are independent 16-bit timers which can select enable seven different operation modes each by the setting of their mode registers. the related registers of timer x and y are listed below. the following register abbreviations are used: ? timer xy control register (txycon: address 0014 16 ) ? port p4 direction register (p4d: address 0009 16 ) ? port p5 direction register (p5d: address 000b 16 ) ? timer x (low-order) (txl: address 0020 16 ) ? timer x (high-order) (txh: address 0021 16 ) ? timer y (low-order) (tyl: address 0022 16 ) ? timer y (high-order) (tyh: address 0023 16 ) ? timer x mode register (txm: address 0027 16 ) ? timer y mode register (tym: address 0028 16 ) ? interrupt edge selection register (intedge: address 003a 16 ) ? interrupt request register 1 (ireq1: address 003c 16 ) ? interrupt request register 2 (ireq2: address 003d 16 ) ? interrupt control register 1 (icon1: address 003e 16 ) ? interrupt control register 2 (icon2: address 003f 16 ) for details, refer to the structures of each register. the following is an explanation of the seven modes: (1) timer ? event counter mode timer mode ? mode selection this mode can be selected by setting "000" to the following bits. timer x operating mode bit (bits 2 to 0) of txm timer y operating mode bit (bits 2 to 0) of tym ? count source selection in high- or middle-speed mode, f(x in )/2, f(x in )/16, or f(x cin ) can be selected as the count source. in low-speed mode the count source is f(x cin ). a count source is selected by the following bit. timer x count source selection bit (bits 7 and 6) of txm timer y count source selection bit (bits 7 and 6) of tym ? interrupt when an underflow is generated, the corresponding timer x interrupt request bit (b4) or timer y interrupt request bit (b5) of ireq1 is set to "1". ? explanation of operation after reset release, timer x stop control bit (b0) and timer y stop control bit (b1) of txycon are set to "1"and the timer stops. during timer stop, a timer value written to the timer x or timer y is set by writing data to the corresponding timer latch and timer at the same time. the timer operation is started by setting the bits 0 or 1 of txycon to "0". when the timer reaches "0000 16 ", an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. for changing a timer value during count operation, a latch value must be changed by writing data only to the corresponding latch first. then the timer is reloaded with the new latch value at the next underflow. event counter mode ? mode selection this mode can be selected by the following sequence. 1. set "000" to the timer x operating mode bit (bits 2 to 0) of txm, or to the timer y operating mode bit (bits 2 to 0) of tym. 2. select an input signal from the cntr 0 pin (in case of timer x ; set "11" to bits 7 and 6 of txm), or from the cntr 1 pin (in case of timer y ; set "11" to bits 7 and 6 of tym) as a count source. the valid edge for the count operation is selected by the cntr 0 / cntr 1 active edge switch bit (b5) of txm or tym: if set to "0", counting starts with the rising edge or if set to "1", counting starts with the falling edge. ? interrupt the interrupt generation at underflow is the same as already explained for the timer mode. ? explanation of operation the operation is the same as already explained for the timer mode. in this mode, the double-function port of cntr 0 /cntr 1 pin must be set to input. figure 19 shows the timing chart for the timer ? event counter mode. (2) pulse output mode ? mode selection this mode can be selected by setting "001" to the following bits. timer x operating mode bit (bits 2 to 0) of txm timer y operating mode bit (bits 2 to 0) of tym ? count source selection in high- or middle-speed mode, f(x in )/2, f(x in )/16, or f(x cin ) can be selected as the count source. in low-speed mode the count source is f(x cin ). ? interrupt the interrupt generation at underflow is the same as already explained for the timer mode. ? explanation of operation counting operation is the same as in timer mode. moreover the pulse which is inverted each time the timer underflows is output from cntr 0 /cntr 1 pin. when the cntr 0 /cntr 1 active edge switch bit (b5) of txm or tym is "0", output starts with "h" level. when set to "1", output starts with "l" level. 20 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group n precautions set the double-function port of cntr 0 /cntr 1 pin to output in this mode. [during timer operation stop] the output from cntr 0 /cntr 1 pin is initialized to the level set through cntr 0 /cntr 1 active edge switch bit. [during timer operation enabled] when the value of the cntr 0 /cntr 1 active edge switch bit is writ- ten over, the output level of cntr 0 /cntr 1 pin is inverted. figure 20 shows the timing chart of the pulse output mode. (3) pulse period measurement mode ? mode selection this mode can be selected by setting "010" to the following bits. timer x operating mode bit (bits 2 to 0) of txm timer y operating mode bit (bits 2 to 0) of tym ? count source selection in high- or middle-speed mode, f(x in )/2 or f(x in )/16 can be selected as the count source. in low-speed mode the count source is f(x cin ). ? interrupt the interrupt generation at underflow is the same as already explained for the timer mode. bits 0 or 1 of ireq2 is set to "1" synchronously to pulse period measurement completion. ? explanation of operation [during timer operation stop] select the count source. next, select the interval of the pulse periods to be measured. when bit 5 of the txm or tym is set to "0", the timer counts during the interval of one falling edge of cntr 0 / cntr 1 pin input until the next falling edge of input. if bits 5 are set to "1", the timer counts during the interval of one rising edge until the next rising edge. [during timer operation enabled] the pulse period measurement starts by setting bit 0 or 1 of txycon to "0" and the timer counts down from the value that was set to the timer before the start of measurement. when a valid edge of measurement start/stop is detected, the 1's complement of the timer value is written to the timer latch and "ffff 16 " is set to the timer. furthermore when the timer underflows, a timer x/y interrupt request occurs and "ffff 16 " is set to the timer. the measured value is held until the next measurement completion. n precautions set the double-function port of cntr 0 /cntr 1 pin to input in this mode. a read-out of timer value is impossible in this mode. the timer is written to only during timer stop (no measurement of pulse periods). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operations during measurement. the timer is set to "ffff 16 " when the timer either underflows or a valid edge of pulse period measurement is detected. due to that, the timer value at the start of measurement depends on the timer value before the start of measurement. figure 19 shows the timing chart of the pulse period measurement mode. (4) pulse width measurement mode ? mode selection this mode can be selected by setting "011" to the following bits. timer x operating mode bit (bits 2 to 0) of txm timer y operating mode bit (bits 2 to 0) of tym ? count source selection in high- or middle-speed mode, f(x in )/2 or f(x in )/16 can be selected as the count source. in low-speed mode the count source is f(x cin ). ? interrupt the interrupt generation at underflow is the same as already explained for the timer mode. bit 0 or 1 of ireq2 is set to "1" syn- chronously to pulse width measurement completion. ? explanation of operation [during timer operation stop] select the count source. next, select the interval of the pulse widths to be measured. when bit 5 of txm or tym is set to "1", the timer counts during the interval of one falling edge of cntr 0 /cntr 1 pin input until the next rising edge of input ("l" interval). if bit 5 is set to "0", the timer counts during the interval of one rising edge until the next falling edge ("h" interval). [during timer operation enabled] the pulse width measurement starts by setting bit 0 or 1 of txycon to "0" and the timer counts down from the value that was set to the timer before the start of measurement. when a valid edge of measurement completion is detected, the 1's complement of the timer value is written to the timer latch and "ffff 16 " is set to the timer. furthermore when the timer underflows, a timer x/y interrupt request occurs and "ffff 16 " is set to the timer. the measured value is held until the next measurement completion. n precautions set the double-function port of cntr 0 /cntr 1 pin to input in this mode. a read-out of timer value is impossible in this mode. the timer is written to only during timer stop (no measurement of pulse widths). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operations during mea- surement. the timer value is set to "ffff 16 " when the timer either underflows or a valid edge of pulse widths measurement is detected. due to that, the timer value at the start of measurement depends on the timer value before the start of measurement. figure 20 shows the timing chart of the pulse width measurement mode. (5) programmable waveform generation mode ? mode selection this mode can be selected by setting "100" to the following bits. timer x operating mode bit (bits 2 to 0) of txm timer y operating mode bit (bits 2 to 0) of tym ? count source selection in high- or middle-speed mode, f(x in )/2, f(x in )/16, or f(x cin ) can be selected as the count source. in low-speed mode the count source is f(x cin ). ? interrupt the interrupt generation at underflow is the same as already 21 3807 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers explained for the timer mode. ? explanation of operation counting operation is the same as in timer mode. moreover the timer outputs the data set in the corresponding output level latch (bit 4 of txm or tym) to cntr 0 /cntr 1 pin each time the timer underflows. after the timer underflows, the generation of optional waveform from cntr 0 /cntr 1 pin is possible through a change of values in the output level latch and timer latch. n precautions set the double-function port of cntr 0 /cntr 1 pin to output in this mode. figure 23 shows the timing chart of the programmable waveform generation mode. (6) programmable one-shot generating mode ? mode selection this mode can be selected by setting "101" to the following bits. timer x operating mode bit (bits 2 to 0) of txm timer y operating mode bit (bits 2 to 0) of tym ? count source selection in high- or middle-speed mode, f(x in )/2 or f(x in )/16 can be selected as the count source. ? interrupt the interrupt generation at underflow is the same as already explained for the timer mode. the one-shot generating trigger condition must be set to the int 0 interrupt edge selection bit (b0) and int 1 interrupt edge selection bit (b1) of intedge. setting these bits to "0" causes the interrupt request being triggered by a falling edge, setting them to "1" causes the interrupt request being triggered by a rising edge. the int 0 interrupt request bit (b0) and int 1 interrupt request bit (b1) of ireq1 are set to "1" by detecting the active edge of the int pin. ? explanation of operation for a "h" one-shot pulse, set bit 5 of txm, tym to "0". [during timer operation stop] the output level of cntr 0 /cntr 1 pin is initialized to "l" at mode selection. set the one-shot pulse width to txh, txl, tyh, tyl. a trigger generation during timer stop (input signal to int 0 /int 1 pin) is invalid. [during timer operation enabled] when a trigger generation is detected, "h" is output, and at underflow "l" is output from cntr 0 /cntr 1 pin. for a "l" one-shot pulse set bit 5 of txm, tym to "1". [during timer operation stop] the output level of cntr 0 /cntr 1 pin is initialized to "h" at mode selection. set the one-shot pulse width to txh, txl, tyh, tyl. a trigger generation during timer stop (input signal to int 0 /int 1 pin) is invalid. [during timer operation enabled] when a trigger generation is detected, "l" is output, and at underflow "h" is output from cntr 0 /cntr 1 pin. n precautions ? set the double-function port of cntr 0 /cntr 1 pin to output and the double-function port of int 0 /int 1 pin to input in this mode. ? this mode is unused in low-speed mode. ? during one-shot generation permission or one-shot generation the output level from cntr 0 /cntr 1 pin changes if the value of the cntr 0 /cntr 1 active edge switch bit is inverted. figure 24 shows the timing chart of the programmable one-shot generating mode. (7) pwm mode ? mode selection this mode can be selected by setting "110" to the following bits. timer x operating mode bit (bits 2 to 0) of txm timer y operating mode bit (bits 2 to 0) of tym ? count source selection in high- or middle-speed mode, f(x in )/2 or f(x in )/16 can be selected as the count source. ? interrupt with a rising edge of cntr 0 /cntr 1 output, the timer x interrupt request bit (b4) and timer y interrupt request bit (b5) of ireq1 are set to "1". ? explanation of operation pwm waveform is output from cntr 0 pin (in case of timer x) or from cntr 1 pin (in case of timer y). the "h" interval of pwm waveform is determined by the setting value m (m=0 to 255) of txh and tyh and the "l" interval of pwm waveform is determined by the setting value n (n=0 to 255) of txl and tyl. the pwm cycles are: pwm cycle time = (m+n)ts pwm duty = m/(m+n) where: ts: period of timer x/timer y count source [during count operation stop] when a timer value is set to txl, txh, tyl, tyh by writing data to timer and timer latch at the same time. when setting this value, the output of cntr 0 /cntr 1 pin is initialized to the "h" level. [during count operation enabled] by setting the bit 0 or 1 of txycon to "0", an "h" interval of txh or tyh is output first, and after that a "l" level interval of txl or tyl are output next. these operations are repeated continuously. the pwm output is changed after the underflow by setting a timer value, which is set by writing data to the timer latch only, to txl, txh, tyl, tyh. n precautions ? set the double-function port of cntr 0 /cntr 1 pin to output in this mode. ? this mode is unused in low-speed mode. ? when the pwm "h" interval is set to "00 16 ", pwm output is "l". ? when the pwm "l" interval is set to "00 16 ", pwm output is "h". ? when the pwm "h" interval and "l" interval are set to "00 16 ", pwm output is "l". ? when a pwm "h" interval or "l" interval is set to "00 16 " at least for a short time, timer x/timer y interrupt request does not occur. ? when the value set to the timer latch is "00 16 ", the value is unde- fined since the timer counts down by dummy count operation. figure 23 shows the timing chart of the pwm mode. 22 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group n precautions regarding all modes ? timer x, timer y writing control one of the following operation is selected by bit 3 of txm or tym for timer x or timer y. writing data to the corresponding latch and timer at the same time writing data to only corresponding latch when the operation "writing data to only corresponding latch" is selected, the value is set to the timer latch by writing a value to timer x/y address and a timer is renewed at the next underflow. after releasing a reset, "writing the corresponding latch and timer at the same time" is selected. when a value is written to timer x/y address, a value is set to a timer and a timer latch at the same time. when "writing data to only corresponding latch" is selected, if writ- ing to a reload latch and an underflow are performed at the same timing, the timer value is undefined. ? timer x, timer y read control in pulse period measurement mode and pulse width measurement mode the timer value cannot be read-out. in all other modes read- out operations without effect to count operations/stops are possible. however, the timer latch value cannot be read-out. ? precautions regarding the cntr 0 /cntr 1 active edge switch bit and the int 0 /int 1 interrupt edge selection bit: the cntr 0 /cntr 1 active edge switch bit and the int 0 /int 1 interrupt edge selection bit settings have an effect also on each interrupt active edge. 23 3807 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 15. block diagram of timer x and timer y data bus programmable one-shot generating circuit programmable one-shot generating mode cntr 0 active edge switch bit "1" pwm generating circuit "0" pwm mode d t q programmable waveform generating mode s t q q pulse output mode cntr 0 active edge switch bit "0" pulse output mode "1" p4 2 /int 0 programmable one-shot generating mode pwm mode pulse width measurement mode pulse period measurement mode output level latch int 0 interrupt request timer x interrupt request cntr 0 interrupt request f(x in )/2 f(x in )/16 f(x cin ) timer x stop control bit timer x count source selection bits p5 4 /cntr 0 cntr 0 active edge switch bit "0" "1" p5 4 latch timer x operating mode bits "001" "100" "101" "110" "1" "0" "0" "1" p4 3 /int 1 int 1 interrupt request timer y interrupt request cntr 1 interrupt request f(x in )/2 f(x in )/16 f(x cin ) p5 5 /cntr 1 cntr 1 active edge switch bit "0" "1" p5 5 latch "001" "100" "101" "110" p5 5 direction register p5 4 direction register edge detection circuit edge detection circuit timer y (low-order) timer y (high-order) timer y latch (high-order) programmable one-shot generating circuit pwm generating circuit programmable one-shot generating mode pwm mode output level latch programmable waveform generating mode pulse output mode programmable one-shot generating mode cntr 1 active edge switch bit pwm mode cntr 1 active edge switch bit pulse output mode d t q s t q q timer y operating mode bits timer y count source selection bits timer y stop control bit pulse width measurement mode pulse period measurement mode timer x (low-order) timer x (high-order) timer x latch (low-order) timer x latch (high-order) timer y latch (low-order) 24 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group fig. 16. structure of timer x mode register, timer y mode register, and timer xy control register timer y mode register (tym : address 0028 16 ) b7 b0 timer x mode register (txm : address 0027 16 ) timer x operating mode bits b2 b1 b0 0 0 0 : timer event counter mode 0 0 1 : pulse output mode 0 1 0 : pulse period measurement mode 0 1 1 : pulse width measurement mode 1 0 0 : programmable waveform generating mode 1 0 1 : programmable one-shot generating mode 1 1 0 : pwm mode 1 1 1 : not used b7 b0 timer x count source selection bits b7 b6 0 0 : f(x in )/2 0 1 : f(x in )/16 1 0 : f(x cin ) 1 1 : input signal from cntr 0 pin cntr 0 active edge switch bit 0 : ?event counter mode ; counts rising edges ?pulse output mode ; output starts with ??level ?pulse period measurement mode ; measures between two falling edges ?pulse width measurement mode ; measures ??periodes ?programmable one-shot generating mode ; after start at ??level, output a ?? pulse (interrupt request is triggered on falling edge) 1 : ?eevent counter mode ; counts falling edges ?pulse output mode ; output starts with ??level ?pulse period measurement mode ; measures between two rising edges ?pulse width measurement mode ; measures ??periodes ?programmable one-shot generating mode ; after start at ??level, output a ??pulse (interrupt request is triggered on rising edge) timer x write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only output level latch 0 : "l" output 1 : "h" output timer y operating mode bits b2 b1 b0 0 0 0 : timer?vent counter mode 0 0 1 : pulse output mode 0 1 0 : pulse period measurement mode 0 1 1 : pulse width measurement mode 1 0 0 : programmable waveform generating mode 1 0 1 : programmable one-shot generating mode 1 1 0 : pwm mode 1 1 1 : not used timer y count source selection bits b7 b6 0 0 : f(x in )/2 0 1 : f(x in )/16 1 0 : f(x cin ) 1 1 : input signal from cntr 1 pin timer y write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only output level latch 0 : "l" output 1 : "h" output cntr 1 active edge switch bit 0 : ?event counter mode ; counts rising edges ?pulse output mode ; output starts with ??level ?pulse period measurement mode ; measures between two falling edges ?pulse width measurement mode ; measures ??periodes ?programmable one-shot generating mode ; after start at ??level, output a ?? pulse (interrupt request is triggered on falling edge) 1 : ?eevent counter mode ; counts falling edges ?pulse output mode ; output starts with ??level ?pulse period measurement mode ; measures between two rising edges ?pulse width measurement mode ; measures ??periodes ?programmable one-shot generating mode ; after start at ??level, output a ??pulse (interrupt request is triggered on rising edge) timer xy control register (txycon : address 0014 16 ) not used (returns ??when read) timer x stop control bit 0 : start counting 1 : stop counting timer y stop control bit 0 : start counting 1 : stop counting b7 b0 25 3807 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 18. timing chart of pulse output mode fig. 17. timing chart of timer?event counter mode ffff 16 0000 16 tl tl: a value set to a timer latch tr: timer interrupt request tr tr tr ffff 16 0000 16 tl tl: a value set to a timer latch tr: timer interrupt request cntr: cntr 0 /cntr 1 interrupt request tr tr tr tr waveform output from cntr 0 /cntr 1 pin cntr cntr this example? condition: cntr 0 /cntr 1 active edge switch bit ?? t output starts with ??level, interrupt at falling edge 26 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group ffff 16 0000 16 t3 tr tr signal input from cntr 0 /cntr 1 pin t2 t1 cntr cntr cntr cntr ffff 16 +t1 t2 t3 ffff 16 tr: timer interrupt request cntr: cntr 0 /cntr 1 interrupt request this example? condition: cntr 0 /cntr 1 active edge switch bit set to ? t measure from rising edge to rising edge; interrupt at rising edge ffff 16 0000 16 t3 tr tr signal input from cntr 0 /cntr 1 pin t2 t1 cntr cntr cntr ffff 16 +t2 t1 t3 tr: timer interrupt request cntr: cntr 0 /cntr 1 interrupt request this example? condition: cntr 0 /cntr 1 active edge switch bit set to ? t measure ??width; interrupt at rising edge fig. 19 timing chart of pulse period measurement mode fig. 20. timing chart of pulse width measurement mode 27 3807 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 22. timing chart of programmable one-shot generating mode fig. 21. timing chart of programmable waveform generating mode ffff 16 0000 16 t3 signal output from cntr 0 /cntr 1 pin t2 t1 t2 t3 l: initial value of timer tr: timer interrupt request cntr: cntr 0 /cntr 1 interrupt request l l t1 tr tr tr tr this example? condition: cntr 0 /cntr 1 active edge switch bit set to ? t output starts with ??level; interrupt at falling edge cntr cntr ffff 16 signal output from cntr 0 /cntr 1 pin l l tr tr tr ll signal input from int 0 /int 1 pin l: one-shot pulse width; timer latch value tr: timer interrupt request cntr: cntr 0 /cntr 1 interrupt request this example? condition: cntr 0 /cntr 1 active edge switch bit set to ? t output a ??pulse; interrupt at falling edge cntr cntr 28 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group fig. 23. timing chart of pwm mode ts timer x/timer y count source timer x/timer y pwm output signal m 5 ts (m+n) 5 ts tr tr pwm waveform (duty : m/(m + n) and period: (m + n) 5 ts) is output m : the setting value of txh/tyh (m = 0 to 255) n: the setting value of txl/tyl (n = 0 to 255) ts: the period of timer x / timer y count source cntr cntr: cntr 0 /cntr 1 interrupt request tr: timer interrupt request this example's condition: cntr 0 /cntr 1 active edge switch bit set to ? t output starts with ??level; interrupt at falling edge n 5 ts 29 3807 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l timer 1, timer 2, timer 3 timer 1 to 3 are 8-bit timers for which the count source can be se- lected through timer 123 mode register. (1) timer 2 write control timer 2 write control bit (b2) of timer 123 mode register allows to select whether a value written to timer 2 is written to timer latch and timer synchronously or to the timer latch only. if only the timer latch is written to, the value is set only to the reload- latch by writing a value to the timer address at that time. the content of timer is reloaded with the next underflow. usually writing operation to the timer latch and timer synchronously is selected. and a value is written to the timer latch and timer synchronously when a value is written to the timer address. if only the timer latch is written to, it may occur that the value set to the counter is not constant, when the timing with which the reload- latch is written to and the underflow timing is nearly the same. (2) timer 2 output control when timer 2 output (t out ) is enabled, inverted signals are output from t out pin each time timer 2 has underflow. for this reason, set the double-function port of t out pin to output mode. n precautions on timers 1 to 3 when the count source for timer 1 to 3 is switched, it may occur that short pulses are generated in count signals and that the timer count value shows big changes. when timer 1 output is selected as timer 2 or timer 3 count source, short pulses are generated to signals output from timer 1 through writing timer 1. due to that, the count values for timer 2 and 3 may change very often. therefore, when the count sources for timer 1 to 3 are set, set the values in order starting from timer 1. fig. 25. block diagram of timer fig. 24. structure of timer 123 mode register timer 1 count source selection bits timer 3 latch (8) timer 3 (8) q q t s "00" p5 0 direction register p5 0 latch "0" "1" t out output active edge switch bit timer 2 write control bit "0" "1" "10" p5 0 /t out timer 3 count source selection bit "0" "1" timer 2 interrupt request timer 3 interrupt request t out output control bit timer 2 count source selection bit timer 1 latch (8) timer 1 (8) timer 1 interrupt request f(x in )/16 (f(x cin )/16 in low-speed mode) f(x in )/16 (f(x cin )/16 in low-speed mode) f(x in )/16 (f(x cin )/16 in low-speed mode) "01" data bus f(x cin ) f(x in )/2 (f(x cin )/2 in low-speed mode) timer 2 latch (8) timer 2 (8) t out output control bit t out output active edge switch bit 0 : start with "h" output 1 : start with "l" output timer 123 mode register (t123m : address 0029 16 ) b7 b0 t out output control bit 0 : t out output disabled 1 : t out output enabled timer 2 write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) not used (returns ??when read) timer 1 count source selection bits 00 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 01 : f(x in )/2 (or f(x cin )/2 in low-speed mode) 10 : f(x cin ) 11 : not available timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 30 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group l real time output port the 3807 group has two on-chip sets of real time output ports (rtp). the two sets of real time output ports consist of two 16-bit timers a and b and eight 8-bit real time port registers. synchronous to the reloading of timers a and b, the real time port register values are output from ports p8 2 to p8 7 , p3 0 and p3 1 . the real time port regis- ters consist of 8-bit register 0 to 7. each port with its corresponding bits is shown in figure 26. timer a and timer b have each two 16-bit timer latches. figure 26 shows the real time port block diagram and figure 27 and 28 show the structure of the real time port control registers 0 to 3. there are four operating modes for real time ports which are: 8 repeated load mode, 6 repeated load mode, 5 repeated load mode and one-shot pulse generating mode. each operating mode can be set for timer a and timer b separately. however, switch modes dur- ing timer count stop. (1) 8 repeated load mode the output operation for each value of the real time port registers 7 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0. the real time port output pointer changes in sequence as a cycle of 8 repeated load opera- tions as "7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, ...." the initial value at the generation of a start trigger can be specified by setting a value in the output pointer. figure 29 shows a timing chart of 8 repeated load mode. (2) 6 repeated load mode the output operation for each value of real time port registers 5 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 to 0. the real time port output pointer changes in sequence as a cycle of 6 repeated load operations as "5, 4, 3, 2, 1, 0, 5, 4, 3, 2, 1, 0, 5, 4, ...." the initial value at the generation of a start trigger can be specified by setting a value in the output pointer. figure 30 shows a timing chart of the 6 repeated load mode. (3) 5 repeated load mode the output operation for each value of real time port registers 4 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0. the real time port output pointer changes in sequence as a cycle of 5 repeated load operations as "4, 3, 2, 1, 0, 4, 3, 2, 1, 0, 4, 3, 2, 1, ...." the initial value at the generation of a start trigger can be specified by setting a value in the output pointer. figure 31 shows a timing chart of the 5 repeated load mode. (4) one-shot pulse generation mode the output operation for each value of real time port registers 2 to 0 is performed only once in association with trigger generation and an underflow of timer latch 1 or 0. after a trigger is generated, the value of real time port register 1 is output from the real time output port and the output pointer value becomes "000 2 ". at each underflow of the timer, the each value of real time port registers 0 and 2 is output in ascending sequence, then the operation is completed. after completion of the operation, the value of real time port register 2 is continuously output from the real time output port and the output pointer value continues to be "001 2 " until the next start trigger is generated. in this condition, the real time port function is in the wait status. when this mode is selected, the pointer value is not changed by writing a value into the output pointer. if external trigger is specified as trigger selection when this mode is selected, a rising and falling double edge trigger is generated regardless of the contents of the int 4 interrupt source bit (b7) of the interrupt edge selection register. figure 32 shows a timing chart of the one-shot pulse generation mode. (5) selection of timer interrupt mode the timer is a count-down system. the contents of the timer latch are reloaded by the count pulse subsequent to the moment when the contents of the counter becomes "0000 16 ". at the same time, the interrupt request bit corresponding to each timer is set to "1." the interrupt request corresponding to the value of the real time port output pointer can also be controlled. for controlling the interrupt request bit, refer to the item pertaining to the timer interrupt mode selection bit of the real time port control register 1,2 shown in figure 27 and 28. (6) switch of timer count source the timer a and the timer b can select the system clock f divided by 2 or 16 as a count source with the timer a, b count source selection bit (b0) of real time port control register 0. [timer latches] each of the timer a and the timer b has two 16-bit timer latches. data is written into the 8 low-order bits and the 8 high-order bits in this order. when the high-order side has been written, the next latch is automatically specified. the writing pointer changes in sequence as "1, 0, 1, 0, 1, ...." the timer latch to be written first can be specified by setting the timer writing pointer. data is not written directly into the timer a and the timer b. when reading the contents of the timer, the count value at that point of time is read. read the high-order side first and then the low-order side. the low-order side value is read with the same timing as that for the high-order side value and held at the timer read latch. the data held state is released by reading the low- order side. at a reload operation of the timer a or the timer b. timer latch 1 is reloaded as the initial value after a trigger is generated. after that, the timer latch is reloaded in sequence as "0, 1, 0, 1, ...." the timer latch value cannot be read out. [start trigger] the operation of the real time port is started by a start trigger. when a start trigger is generated, the value of the real time port register specified by the output pointer (the value of real time port register 1 in the one-shot pulse generation mode) is output from the real time output port. the value of timer latch 1 is reloaded into the timer a or the timer b and the timer count a, b source stop bit is released, so that the timer count is started. after that, when the timer underflows, data is transferred from the real port register to the real time output port. as a start trigger, either internal trigger or external trigger can be selected by the timer a start trigger selection bit (b2) or timer b start trigger selection bit (b5) of real time port control register 0. 31 3807 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers when the internal trigger is selected, a start trigger is generated by an input signal of the int 4 pin. the start trigger becomes a falling edge when the int 4 interrupt edge selection bit is "0" and a rising edge when this bit is "1". when the external trigger is selected in the one-shot pulse genera- tion mode, the start trigger becomes a rising/falling double edge trig- ger regardless of the contents of the int 4 interrupt edge selection bit. [real time port registers] rtp the data to be output to real time ports is written into 8 real time port registers 0 to 7. the correspondence between each bit of real time port registers and each port output is as follows : p3 1 : bit 7 of real time port registers 7 to 0 p3 0 : bit 6 of real time port registers 7 to 0 p8 7 : bit 5 of real time port registers 7 to 0 p8 6 : bit 4 of real time port registers 7 to 0 p8 5 : bit 3 of real time port registers 7 to 0 p8 4 : bit 2 of real time port registers 7 to 0 p8 3 : bit 1 of real time port registers 7 to 0 p8 2 : bit 0 of real time port registers 7 to 0 it can be selected for each bit by real time port control register 3 whether the output of each port is to be used as an ordinary i/o port or a real time port output. [real time port data pointer] it can be optionally specified by the real time port data pointers a or b and the real time port data pointer a or b switching bit in which real time port register the output data is to be set or form which real time port register the data output is to be started. when writing output data into the real time port register, set the real time port data pointer a, b switch bit to "0" (select the r/w pointer) and also write a value into the 3 bits of the real time port data pointers a, b. with this, the real time port register for writing will be specified. after that, when a value is written into the real time port register (address 002a 16 ), the data is written into the specified real time port register and also the r/w pointer value is automatically decreased by 1. then writing data is enabled into the next real time port register. a value of "000 2 " to "111 2 " can be set int the r/w pointer regardless of the operating mode specified by the timer a, b operating mode selection bit, and the r/w pointer value is automatically decreased by 1 by writing data into the real time port register. however, when a value becomes "000 2 ", the r/w pointer value is decreased by 1 in the numeral range of stages to be used in each operating mode un- less the r/w pointer is set again at the subsequent write operation to the real time port register. when "111 2 (=7)" is set in the r/w pointer, the r/w pointer operation in each selected mode is as follows : ?during 8 repeated load mode 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 y 7 y 6 y 5... ?during 6 repeated load mode 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 y 5 y 4 y 3... ?during 5 repeated load mode 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 y 4 y 3 y 2.... ?during one-shot pulse generation mode 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 y 2 y 1 y 0.... when reading the real time port register, set the real time port data pointer a, b switch bit to "0" (select the r/w pointer) and also writing a value into the 3 bits of the real time port data pointer a, b to specify the real time port register for reading. after that, the value of the specified real time port register can be read by reading the real time port register (address 002a 16 ). in this care, however, the r/w pointer value is not counted down automatically. accordingly, to read an- other real time port register, rewrite the r/w pointer beforehand. to specify a read port register to be output to the real time output port, set the real time port data pointer a, b switch bit to "1" (select an output pointer) and also set a value in the 3 bits of the real time port data pointer a or b. when a start trigger is generated, data is output beginning with the real time port register set in the output pointer and the output pointer value is automatically decreased by 1. at each underflow of the timer a or timer b, the output pointer value is automatically decreased by 1. regarding the case of the one-shot pulse generation mode, however, refer to the item pertaining to the one-shot pulse generation mode. when the real time port data pointer a to b has been read, only the output pointer can be read. n notes regarding all modes ?when the trigger is generated again during timer count operation, the operation is started from the beginning. in this case, put an interval of 3 cycles or more between the generation of a trigger and the generation of the next trigger, if the generation of the next trig- ger occurs almost concurrently with the underflow timing of the timer, the next real time output may not be performed normally. ?to stop the timer count after generation of a start trigger, write "1" in the timer a, b count source stop bit of real time port control register 0 at an interval of 3 cycles or more of the timer count source. ?to change the contents of the real time port data pointer a, b switch bit, the real time port data pointer must be specified simultaneously. therefore, use the ldm/sta instruction instead of the seb/clb instruction. ?if the timer a, b count source stop bit is changed ("1" y "0") by a start trigger between the read operation and the write operation of a read-modify-write instruction such as the seb instruction which is used in real time port control register 0, the timer count will stop, having an effect on the real time output. an maximum interval of 2 cycles of the count source is required before the timer a, b count source stop bit is cleared to "0" which indicates the count operation state after a start trigger is generated regardless of whether the start trigger is an internal trigger or an external trigger. accordingly, do not use the read-modify-write instruction for real time port control register 0 in this period. if a write operation for real time port control register 0 with any purpose other than stopping the timer count is performed concurrently with the generation of a start trigger, be sure to use such an instruction for writing "0" into the timer a, b count source stop bit as the ldm/sta instruction. even if "0" is written into the timer a, b count source stop bit, the timer count remains in the stop state without change. ?when the timing for writing to the high-order side reload latch is almost equal to the underflow timing, an undesirable value may be set in the timer a or timer b. ?if the real time output port is selected by real time port control regis- ter 3 after resetting, "l" is output from this pin until a start trigger is generated. 32 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group data bus p3 1 latch p3 1 direction register p3 0 latch p3 0 direction register p8 7 /rtp 5 p8 7 latch p8 7 direction register p8 6 /rtp 4 p8 6 latch p8 6 direction register x in 1/16 x cin "10" "00" "01" main clock division ratio selection bits "1" "0" timer a, b count source selection bit 1/2 timer b interrupt request timer a interrupt request p8 5 /rtp 3 real time output real time port output selection bit (p8 5 ) p8 5 latch p8 5 direction register p8 4 /rtp 2 p8 4 latch p8 4 direction register p8 3 /rtp 1 real time output real time port output selection bit (p8 3 ) p8 3 latch p8 3 direction register p8 2 /rtp0 p8 2 latch pwm 0 ?o? pwm 1 ?o? 0 1 state transition of timer count source stop bit operation stop timer count source stop bit is set to "1". at reset when an external start trigger is generated (external trigger is selected) when a start trigger bit is set to "1" (internal trigger is selected) a timer latch value is loaded into the timer p8 2 direction register real time output real time port output selection bit (p8 2 ) real time output real time port output selection bit (p8 4 ) real time output real time port output selection bit (p8 6 ) real time output real time port output selection bit (p8 7 ) real time port register 4 (8) real time port register 5 (8) real time port register 6 (8) real time port register 7 (8) real time port register 0 (8) real time port register 1 (8) real time port register 2 (8) real time port register 3 (8) "0" "1" output latch (8) timer b 0h latch (8) timer b 1h latch (8) timer b 0l latch (8) timer b 1l latch (8) timer b count source stop bit timer a count source stop bit timer a (16) timer a 1h latch (8) timer a 1l latch (8) "0" "1" 0 7 timer b (16) a timer latch value is loaded into the timer p5 0 /rtp0 /pwm 0 p3 1 /rtp 7 p3 0 /rtp 6 real time port r/w pointer a (3) real time port output pointer a (3) real time port output pointer b (3) timer a write pointer (1) timer b write pointer (1) timer b read-out latch (8) real time port r/w pointer b (3) real time port ?port allocation selection bit timer a 0h latch (8) timer a 0l latch (8) timer a read-out latch (8) real time port ?port allocation selection bit real time output real time port output selection bit ( p3 1) real time output real time port output selection bit ( p3 0) fig. 26. block diagram of real time output port 33 3807 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers note: rising or falling edge of external input can be switched by the int 4 interrupt edge selection bit of interrupt edge selection register (however, at one-shot pulse generating mode the timer is triggered at both rising and falling edge). timer a interrupt mode selection bit 0: interrupt request occurs with rtp output pointer value ?00 2 1: interrupt request occurs regardless of rtp output pointer value timer a operation mode selection bit 00: 8 repeated load mode 01: 6 repeated load mode 10: 5 repeated load mode 11: one-shot pulse generating mode real time port control register 1 (rtpcon1 : address 002c 16) real time port data pointer a (output pointer value at read-out) 000: indicates real time port register 0 001: indicates real time port register 1 010: indicates real time port register 2 011: indicates real time port register 3 100: indicates real time port register 4 101: indicates real time port register 5 110: indicates real time port register 6 111: indicates real time port register 7 timer a write pointer 0: indicates timer a0 latch 1: indicates timer a1 latch b7 real time port control register 0 (rtpcon0 : address 002b 16 ) timer a, b count source selection bit 0: f(x in )/2 or f(x cin )/2 1: f(x in )/16 or f(x cin )/16 timer b start trigger bit (??at read-out) 0: not triggered 1: timer b start (when bit 5=?? timer a start trigger selection bit 0: internal trigger (trigger is generated by setting bit 3 to ?? 1: external trigger (trigger start by external input int 4 ) (note) timer a start trigger bit (??at read-out) 0: not triggered 1: timer a start (when bit 2=?? real time port ?port allocation selection bit 0: 4-4 port division (p8 2 to p8 5 correspond to timer a; p8 6 , p8 7 , p3 0 , p3 1 correspond to timer b) 1: 2-6 port division (p8 2 to p8 7 correspond to timer a; p3 0 , p3 1 correspond to timer b) timer b count source stop bit 0: count operation (when a start trigger is generated, ??is set automatically) 1: count stop timer a count source stop bit 0: count operation (when a start trigger is generated, ??is set automatically) 1: count stop b7 real time port data pointer a switch bit (??at read-out ) 0: r/w pointer 1: output pointer b0 timer b start trigger selection bit 0: internal trigger (trigger is generated by setting bit 6 to ?? 1: external trigger (trigger start by external input int 4 ) (note) b0 fig. 27. structure of real time output port related register (1) 34 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group fig. 28 structure of real time output port related register (2) timer b interrupt mode selection bit 0: interrupt request occurs with rtp output pointer value ?00 2 1: interrupt request occurs regardless of rtp output pointer value real time port control register 2 (rtpcon2 : address 002d 16) real time port data pointer b (output pointer value at read-out) 000: indicates real time port register 0 001: indicates real time port register 1 010: indicates real time port register 2 011: indicates real time port register 3 100: indicates real time port register 4 101: indicates real time port register 5 110: indicates real time port register 6 111: indicates real time port register 7 timer b write pointer 0: indicates timer b0 latch 1: indicates timer b1 latch b7 real time port control register 3 (rtpcon3 : address 002e 16 ) real time port output selection bit (p8 2 ) 0: i/o port 1: real time output port real time port output selection bit (p8 3 ) 0: i/o port 1: real time output port real time port output selection bit (p8 4 ) 0: i/o port 1: real time output port real time port output selection bit (p8 5 ) 0: i/o port 1: real time output port real time port output selection bit (p8 6 ) 0: i/o port 1: real time output port real time port output selection bit (p8 7 ) 0: i/o port 1: real time output port real time port output selection bit (p3 0 ) 0: i/o port 1: real time output port real time port output selection bit (p3 1 ) 0: i/o port 1: real time output port real time port data pointer b switch bit (??at read-out ) 0: r/w pointer 1: output pointer b7 b0 timer b operating mode selection bit 00: 8 repeated load mode 01: 6 repeated load mode 10: 5 repeated load mode 11: one-shot pulse generating mode b0 35 3807 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 30. 6 repeated load mode operation fig. 29. 8 repeated load mode operation timer a count value port p8 2 / rtp 0 port p8 3 / rtp 1 synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. timer count source stop bit timer a operating mode selection bit: in case of 8 repeated load mode port p8 4 / rtp 2 port p8 5 / rtp 3 7 6543210765 11000001110 01110000011 00011100000 00000111000 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 a 1 real time port output pointer a #7 #6 #5 #4 #3 #2 #1 #0 #7 #6 #5 4 #7?: data of real time port registers 7 to 0 4-4 port division timer a operating mode selection bit: in case of 6 repeated load mode timer a count value port p8 2 / rtp 0 port p8 3 / rtp 1 synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. timer count source stop bit port p8 4 / rtp 2 5 432 1054321 real time port output pointer a 11 00 01 11 00 0 01 11 00 01 11 0 00 01 11 00 01 1 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 a 1 #5 #4 #3 #2 #1 #0 #5 #4 #3 #2 #1 0 #5?: data of real time port registers 5 to 0 4-4 port division (3 ports out of p8 2 /rtp 0 to p8 5 /rtp 3 are used) 36 mitsubishi microcomputers single-chip 8-bit cmos microcomputer 3807 group fig. 31. 5 repeated load mode operation timer a operating mode selection bit: in case of 5 repeated load mode synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. 4 3210432 10 10 00 11 00 01 11 00 01 1 00 0 01 10 00 11 00 00 11 0 00 1 10 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 timer a count value port p8 2 / rtp 0 port p8 3 / rtp 1 timer count source stop bit port p8 4 / rtp 2 port p8 5 / rtp 3 real time port output pointer a port p8 6 / rtp 4 00 01 10 00 11 #4 #3 #2 #1 #0 #4 #3 #2 #1 #0 4 #4?: data of real time port registers 4 to 0 2-6 division (5 ports out of p8 2 /rtp 0 to p8 7 /rtp 5 are used) timer a count value synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. timer count source stop bit real time port output pointer a timer a operating mode selection bit: in case of one-shot pulse generating mode port p8 2 / rtp 0 external start trigger input int 4 11 1 00 1 0 0 0 1 1 0 a1 a0 a1 a0 counting stops when timer a0 latch has underflow 02 02 port p8 3 / rtp 1 11 #1 #0 #1 #0 #2 #2?: data of real time port registers 2 to 0 #2 counting stops when timer a0 latch has underflow fig. 32. one-shot pulse generating mode operation 37 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer serial i/o l serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation during serial i/o1 opera- tion. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit (b6) of the serial i/o1 control register to "1." for clock synchronous serial i/o, the transmitter and the receiver must use the same clock for serial i/o1 operation. if an internal clock is used, transmit/receive is started by a write signal to the transmit/receive buffer register (tb/rb) (address:0018 16 ). 1/4 x in 1/4 f/f p4 6 /s clk1 serial i/o1 status register serial i/o 1 control register p4 7 /s rdy1 p4 4 /r x d p4 5 /t x d f(x in ) (f(x cin ) in low-speed mode) receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit baud rate generator division ratio 1/(n+1) address 001c 16 brg count source selection bit clock control circuit falling edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transmit/receive shift clock (1/2 1/2048 of internal clock or external clock) serial output txd serial input rxd write-in signal to transmit/receive buffer register (address 0018 16 ) overrun error (oe) detection notes 1 : the transmit interrupt (ti) can be selected to occur either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . receive enable signal s rdy1 fig. 34. operation of clock synchronous serial i/o1 function fig. 33. block diagram of clock synchronous serial i/o1 38 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer (2) asynchronous serial i/o (uart) mode asynchronous serial i/o1 mode (uart) can be selected by clear- ing the serial i/o1 mode selection bit (b6) of the serial i/o1 control register to "0." eight serial data transfer formats can be selected and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next charac- ter is being received. f(x in ) 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 stdetector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bit 8 bit (f(x cin ) in low-speed mode) serial i/o1 control register p4 6 /s clk1 serial i/o1 status register p4 4 /r x d p4 5 /t x d fig. 35. block diagram of uart serial i/o1 tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1* st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock write-in signal to transmit buffer register serial output t x d read-out signal from receive buffer register serial input r x d * generated at 2nd bit in 2-stop bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit 1: error flag detection occurs at the same time that the rbf flag becomes "1" (at 1st stop bit, during reception). 2: the transmit interrupt (ti) can be selected to occur when either the tbe or tsc flag becomes "1", depending on the setting o f the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes "1". 4: after data is written to the transmit buffer register when tsc=1, 0.5 to 1,5 cycles of the data shift cycle is necessary un til changing to tsc=0. notes fig. 36. operation of uart serial i/o1 function 39 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer [ transmit buffer register/receive buffer register ] tb/rb (0018 16 ) the transmit buffer and the receive buffer are located in the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is "0". [serial i/o 1 status register] sio1sts (0019 16 ) the read-only serial i/o1 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (b4 to b6) are only valid in uart mode. the receive buffer full flag (b1) is cleared to "0" when the receive buffer is read. the error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a writing to the serial i/o1 status regis- ter clears all the error flags oe, pe, fe, and se (b3 to b6, respec- tively). writing "0" to the serial i/o1 enable bit (sioe : b7 of the serial i/o1 control register) also clears all the status flags, including the error flags. all bits of the serial i/o1 status register are initialized to "0" at reset, but if the transmit enable bit (b4) of the serial i/o1 control register has been set to "1", the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become "1." [serial i/o1 control register] sio1con (001a 16 ) the serial i/o1 control register contains eight control bits for serial i/o1 functions. [uart control register] uartcon (001b 16 ) the uart control register consists of four control bits (b0 to b3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. one bit in this register (b4) is always valid and sets the output structure of the p4 5 /txd pin. [baud rate generator] brg (001c 16 ) the baud rate generator determines the baud rate for serial transfer. with the 8-bit counter having a reload register the baud rate genera- tor divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift register shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns "1" when read) serial i/o1 status register (sio1sts : address 0019 16 ) serial i/o1 control register (sio1con : address 001a 16 ) b0 b0 brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-peed mode) 1: f(x in )/4 ((x cin )/4 in low-speed mode) serial i/o1 synchronous clock selection bit (scs) 0: brg/ 4 (when clock synchronous serial i/o is selected) brg/16 (uart is selected) 1: external clock input (when clock synchronous serial i/o is selected) external clock input/16 (uart is selected) s rdy1 output enable bit (srdy) 0: p4 7 pin operates as ordinaly i/o pin 1: p4 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p4 4 to p4 7 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p4 4 to p4 7 operate as serial i/o pins) b7 uart control register (uartcon : address 001b 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity cheching disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) not used (return "1" when read) b0 fig. 37. structure of serial i/o1 related register 40 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer l serial i/o2 the serial i/o2 can be operated only as the clock synchronous type. as a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial i/o2 synchronous clock selection bit (b6) of serial i/o2 control register 1. the internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selec- tion bit (b2, b1, b0) of serial i/o2 control register 1. regarding s out2 and s clk2 being output pins, either cmos output format or n-channel open-drain output format can be selected by the p7 1 /s out2 , p7 2 /s clk2 p-channel output disable bit (b7) of serial i/o2 control register 1. when the internal clock has been selected, a transfer starts by a write signal to the serial i/o2 register (address 001f 16 ). after comple- tion of data transfer, the level of the s out2 pin goes to high imped- ance automatically but bit 7 of the serial i/o2 control register 2 is not set to "1" automatically. when the external clock has been selected, the contents of the serial i/o2 register is continuously sifted while transfer clocks are input. accordingly, control the clock externally. note that the s out2 pin does not go to high impedance after completion of data trans- fer. to cause the s out2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial i/o2 control register 2 to "1" when s clk2 is "h" after completion of data transfer. after the next data transfer is started (the transfer clock falls), bit 7 of the serial i/o2 control register 2 is set to "0" and the s out2 pin is put into the active state. regardless of the internal clock to external clock, the interrupt re- quest bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. in case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial i/o2 register becomes a fractional number of bits close to msb if the transfer direction selection bit of serial i/o2 control register 1 is lsb first, or a fractional number of bits close to lsb if the said bit is msb first. for the remaining bits, the previously re- ceived data is shifted. at transmit operation using the clock synchronous serial i/o, the s cmp2 signal can be output by comparing the state of the transmit pin s out2 with the state of the receive pin s in2 in synchronization with a rise of the transfer clock. if the output level of the s out2 pin is equal to the input level to the s in2 pin, "l" is output from the s cmp2 pin. if not, "h" is output. at this time, an int 2 interrupt request can also be generated. select a valid edge by bit 2 of the interrupt edge selection register (address 003a 16 ). [serial i/o2 control registers 1, 2] sio2con1 / sio2con2 the serial i/o2 control registers 1 and 2 are containing various se- lection bits for serial i/o2 control as shown in figure 40. fig. 38 structure of serial i/o2 control registers 1, 2 serial i/o2 control register 1 (sio2con1 : address 001d 16 ) serial i/o2 control register 2 (sio2con2 : address 001e 16 ) b7 b7 b0 optional transfer bits b2 b1 b0 0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit not used ( returns "0" when read) serial i/o2 i/o comparison signal control bit 0: p5 1 i/o 1: s cmp2 output s out2 pin control bit (p7 1 ) 0: output active 1: output high-impedance internal synchronous clock selection bit b2 b1 b0 0 0 0: f(x in )/8 (f(x cin )/8 in low-speed mode) 0 0 1: f(x in )/16 (f(x cin )/16 in low-speed mode) 0 1 0: f(x in )/32 (f(x cin )/32 in low-speed mode) 0 1 1: f(x in )/64 (f(x cin )/64 in low-speed mode) 1 1 0: f(x in )/128 f(x cin )/128 in low-speed mode) 1 1 1: f(x in )/256 (f(x cin )/256 in low-speed mode) serial i/o2 port selection bit 0: i/o port 1: s out2 ,s clk2 output pin s rdy2 output enable bit 0: p7 3 pin is normal i/o pin 1: p7 3 pin is s rdy2 output pin transfer direction selection bit 0: lsb first 1: msb first serial i/o2 synchronous clock selection bit 0: external clock 1: internal clock p7 1 /s out2 , p7 2 /s clk2 p-channel output disable bit 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode ) b0 41 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer x in "1" "0" "0" "1" "0" "1" s rdy2 s clk2 "0" "1" 1/8 1/16 1/32 1/64 1/128 1/256 "1" "0" x cin "10" "00" "01" data bus serial i/o2 interrupt request serial i/o2 port selection bit serial i/o counter 2 (3) serial i/o2 register (8) synchronous circuit serial i/o2 port selection bit serial i/o2 synchronous clock selection bit s rdy2 output enable bit external clock internal synchronous clock selection bit divider optional transfer bits (3) p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p7 2 latch p7 1 latch p7 3 latch p7 3 /s rdy2 p5 1 /s cmp2 /int 2 serial i/o2 i/o comparison signal control bit p5 1 latch q d main clock division ratio selection bits (note) note: either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of cpu mode register. fig. 40. timing chart of serial i/o2 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (note 1) serial i/o2 output s out2 serial i/o2 input s in2 receive enable signal s rdy2 write-in signal to serial i/o2 register (note 2) serial i/o2 interrupt request bit set . 1: when the internal clock is selected as a transfer clock, the f(x in ) clock division (f(x cin ) in low-speed mode) can be selected by setting bits 0 to 2 of serial i/o2 control register 1. 2: when the internal clock is selected as a transfer clock, the s cout2 pin has high impedance after transfer completion. notes fig. 39. block diagram of serial i/o2 42 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer s clk2 s in2 s out2 s cmp2 judgement of i/o data comparison fig. 41 s cmp2 output operation 43 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer a-d converter [a-d conversion register] ad (address 0035 16 ) the a-d conversion register is a read-only register that contains the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. [a-d control register] adcon the a-d control register controls the a-d conversion process. bits 0 to 3 of this register select specific analog input pins. bit 4 signals the completion of an a-d conversion. the value of this bit remains at "0" during an a-d conversion, then changes to "1" when the a-d conver- sion is completed. writing "0" to this bit starts the a-d conversion. when bit 6, which is the ad external trigger valid bit, is set to "1", this bit enables a-d conversion at a falling edge of an adt input. set ports which is also used as adt pins to input when using an a-d external trigger. bit 5 is the adv ref input switch bit. writing "1" to this bit, this bit always causes adv ref connection. writing "0" to this bit causes adv ref connection only during a-d conversion and cut off when a-d conversion is completed. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and adv ref by 256, and outputs the divided voltages. [channel selector] the channel selector selects one of the input ports an 12 to an 0 and inputs it to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad conversion interrupt request bit to "1." note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 500khz during a-d conversion. use a cpu system clock dividing the main clock x in as the internal clock f . n note when the a-d external trigger is invalidated by the ad external trigger valid bit, any interrupt request is not generated at a fall of the adt input. when the ad external trigger valid bit is set to "1" before- hand, a-d conversion is not started by writing "0" into the ad conver- sion completion bit and "0" is not written into the ad conversion completion bit. do not set "0" in the ad conversion completion bit concurrently with the timing at which the ad external trigger valid bit is rewritten. put an interval of at least 50 cycles to more of the internal clock f between a start of a-d conversion and the next start of a-d conversion. a-d control register (adcon : address 0034 16 ) analog input pin selection bit 0000: p7 3 /s rdy2 /adt/an 0 0001: p7 4 /an 1 0010: p7 5 /an 2 0011: p7 6 /an 3 0100: p7 7 /an 4 0101: p6 0 /an 5 0110: p6 1 /an 6 0111: p6 2 /an 7 1000: p6 3 /cmp in /an 8 1001: p6 4 /cmp ref /an 9 1010: p6 5 /dav ref /an 10 1011: p8 0 /da 3 /an 11 1100: p8 1 /da 4 /an 12 ad conversion completion bit 0: conversion in progress 1: conversion completed adv ref input switch bit 0: off 1: on ad external trigger valid bit 0: a-d external trigger invalid 1: a-d external trigger valid interrupt source selection bit 0: interrupt request at a-d conversion completed 1: interrupt request at adt input falling b7 b0 a-d control register channel selector a-d control circuit a-d conversion register resistor ladder av ss adv ref comparator adt/a-d interrupt request b7 b0 data bus 4 8 p7 3 /s rdy2 /adt/an 0 p7 4 /an 1 p7 5 /an 2 p7 6 /an 3 p7 7 /an 4 p6 0 /an 5 p6 1 /an 6 p6 2 /an 7 p6 3 /cmp in /an 8 p6 4 /cmp ref /an 9 p6 5 /dav ref /an 10 p8 0 /da 3 /an 11 p8 1 /da 4 /an 12 fig. 42. structure of a-d control register fig. 43. block diagram of a-d converter 44 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer d-a control register (dacon : address 0033 16 ) da 1 output enable bit da 2 output enable bit da 3 output enable bit da 4 output enable bit not used (return "0" when read) 0 : output disabled 1 : output enabled b7 b0 av ss p6 5 /dav ref /an 10 "0" "1" msb "0" "1" r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r lsb 2r p5 6 /da 1 p5 7 /da 2 p8 0 /da 3 /an 11 p8 1 /da 4 /an 12 d-a i conversion register (note) da i output enable bit (note) note: i=1 to 4 fig. 46. equivalent connection circuit of d-a converter d-a converter the 3807 group has an on-chip d-a converter with 8-bit resolution and 4 channels (dai (i=14)). the d-a converter is performed by setting the value in the d-a conversion register. the result of d-a converter is output from dai pin by setting the dai output enable bits to "1." when using the d-a converter, the corresponding port direc- tion register bit (p6 5 /dav ref /an 10 , p5 6 /da 1 , p5 7 /da 2 , p8 0 /da 3 /an 11 , p8 1 /da 4 /an 12 ) should be set to "0" (input status). the output analog voltage v is determined by the value n (base 10) in the d-a conversion register as follows: v=dav ref x n/256 (n=0 to 255) where dav ref is the reference voltage. at reset, the d-a conversion registers are cleared to "00 16 ", the dai output enable bits are cleared to "0", and dai pin is set to input (high impedance). the da output is not buffered, so connect an external buffer when driving a low-impedance load. d-a1 conversion register (0036 16 ) d-a2 conversion register (0037 16 ) d-a3 conversion register (0038 16 ) d-a4 conversion register (0039 16 ) p5 6 /da 1 p5 7 /da 2 p8 0 /da 3 /an 11 p8 1 /da 4 /an 12 data bus d-a i conversion register (8) r-2r resistor ladder da i output enable bit fig. 44. structure of d-a control register fig. 45. block diagram of d-a converter 45 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer analog comparator an analog comparator circuit which is independent of peripheral cir- cuits in the microcomputer is incorporated ( note ). an analog comparator outputs the result of comparison with an input voltage of cmp ref pin which is specified as a reference voltage and an input voltage of cmp in pin to cmp out pin. the result is "1" when the input voltage to port cmp in is higher than the voltage applied to port cmp ref and "0" when the voltage is lower. because the analog comparator consists of an analog mos circuit, set the input voltage to the cmp in pin and the cmp ref pin within the following range : v ss +1.2 v to cmpv cc C0.5v n note the analog comparator circuit is separated from the mcu internal peripheral circuit in the microcomputer. accordingly, even if the mi- crocomputer runs away, the analog comparator is still in operation. for this reason, the analog comparator can be used for safety circuit design. fig. 47. block diagram of analog comparator p6 3 /cmp in /an 8 p6 4 /cmp ref /an 9 cmp out + cmpv cc av ss 46 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer (2) watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 0017 16 ) permits selecting a watchdog timer h count source. when this bit is set to "0", the count source becomes the underflow signal of watchdog timer l. the detection time is set then to f(x in )=131.072 ms at 8 mhz frequency and f(x cin )=32.768 s at 32 khz frequency. when this bit is set to "1", the count source becomes the signal divided by 16 for f(x in ) (or f(x cin )). the detection time in this case is set to f(x in )=512 m s at 8 mhz frequency and f(x cin )=128 ms at 32 khz frequency. this bit is cleared to "0" after resetting. (3) operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 0017 16 ) permits disabling the stp instruction when the watchdog timer is in opera- tion. when this bit is "0", the stp instruction is enabled. when this bit is "1", the stp instruction is disabled. once the stp instruction is executed, an internal resetting takes place. when this bit is set to "1", it cannot be rewritten to "0" by program. this bit is cleared to "0" after resetting. watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and a 8-bit watchdog timer h. l standard operation of watchdog timer when any data is not written into the watchdog timer control register (address 0017 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0017 16 ) and an internal resetting takes place at an underflow of the watchdog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0017 16 ) may be started before an underflow. when the watchdog timer control register (address 0017 16 ) is read, the values of the 6 high-order bits of the watchdog timer h, stp instruction disable bit, and watchdog timer h count source selection bit are read. (1) initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0017 16 ), each watchdog timer h and l is set to "ff 16 ." x in data bus x cin "10" "00" "01" main clock division ratio selection bits (note) "0" "1" 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ?f 16 ?is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of cpu mode register. stp instruction ?f 16 ?is set when watchdog timer control register is written to. fig. 48. block diagram of watchdog timer b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 0017 16 ) b7 fig. 49. structure of watchdog timer control register 47 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer b0 port p2p3 control register (p2p3c : address 0015 16 ) b7 p3 4 clock output control bit 0: i/o port 1: clock output output clock frequency selection bits 000: f 001: f(x cin ) 010: "l" fixed for output 011: "l" fixed for output 100: f(x in ) (f(x cin ) in low-speed mode) 101: f(x in )/2 (f(x cin )/2 in low-speed mode) 110: f(x in )/4 (f(x cin )/4 in low-speed mode) 111: f(x in )/16 (f(x cin )/16 in low-speed mode) not used (return "0" when read) p2?3 2 input level selection bit 0: cmos level input 1: ttl level input clock output function the internal clock f can be output from i/o port p3 4 . control of i/o ports and clock output function can be performed by port p2p3 control register (address 0015 16 ). (1) i/o ports or clock output function selection the p3 4 clock output control bit (b0) of port p2p3 control register selects the i/o port or clock output function. when clock output function is selected, the clock is output regardless of the port p3 4 direction register settings. directly after bit 0 is written to, the port or clock output is switched synchronous to a falling edge of clock frequency selected by the output clock frequency selection bit. when memory expansion mode or microprocessor mode is selected in cpu mode register (b1, b0), clock output is selected on regardless of p3 4 clock output control bit settings or port p3 4 direction register settings. (2) selection of output clock frequency the output clock frequency selection bits (b3, b2, b1) of port p2p3 control register select the output clock frequency. the output waveform when f(x in ) or f(x cin ) is selected, depends on x in or x cin input waveform however; all other output waveform settings have a duty cycle of 50%. note: either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of cpu mode register. p3 4 port latch p3 4 /ck out / 1/2 "110" "100" output clock frequency selection bits x in 1/4 "101" "111" 1/16 "000" x cin "001" main clock division ratio selection bits (note) low-speed mode p3 4 direction register p3 4 clock output control bit microprocessor mode/memory expansion mode "010" "011" high-speed or middle-speed mode fig. 51. block diagram of clock output function fig. 50. structure of port p2p3 control register 48 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer reset circuit ______ to reset the microcomputer, reset pin should be held at an "l" ______ level for 2 m s or more. then the reset pin is returned to an "h" level (the power source voltage should be between 2.7 v and 5.5 v, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.54 v for v cc of 2.7 v. (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.7 v reset internal reset data f address sync x in : 10.5 to 18.5 clock cycles x in ? ? ? ? ? fffc fffd ad h , l ? ? ? ? ? ad l ad h 1: the frequency relation of f(x in ) and f( f ) is f(x in )=8 ? f( f ). 2: the question marks (?) indicate an undefined state that depends on the previous state. reset address from the vector table. notes fig. 52. reset circuit example fig. 53. reset sequence 49 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 fffc 16 contents ff 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 (ps) (pc h ) (pc l ) * the initial values depend on level of port cnv ss. x: not fixed since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. address register contents address register contents 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 ff 16 01 16 00 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0014 16 0015 16 0016 16 0017 16 0019 16 001a 16 001b 16 001d 16 001e 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 timer x (low-order) timer 2 port p0 port p0 direction register port p1 port p1 direction register port p2 port p2 direction register port p3 port p3 direction register port p4 port p4 direction register port p5 port p5 direction register port p6 port p6 direction register port p7 port p7 direction register port p8 port p8 direction register timer xy control register port p2p3 control register pull-up control register watchdog timer control register serial i/o1 status register serial i/o1 control register uart control register serial i/o2 control register 1 serial i/o2 control register 2 timer x (high-order) timer y (low-order) timer y (high-order) timer 1 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) program counter timer 3 interrupt edge selection register timer x mode register timer y mode register timer 123 mode register real time port register 07 real time port control register 0 real time port control register 1 r/w pointer output pointer real time port control register 2 r/w pointer output pointer real time port control register 3 timer a (low-order) timer a (high-order) timer b (low-order) timer b (high-order) d-a control register a-d control register d-a1 conversion register d-a2 conversion register d-a3 conversion register d-a4 conversion register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 processor status register 1 000 0 00 16 111 00 16 00 16 00 16 fffd 16 contents 5 1 5 5 5 5 5 5 010010 0 * 000100 0 0 111 111 111 1 000 0 100100 0 0 000000 1 1 00000 0 0 * 001111 1 1 100000 0 0 111000 0 0 000001 1 1 fig. 54. internal status at reset 50 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer ("0") before executing the stp instruction. oscillator restarts when an external interrupt is received, but the internal clock f is not sup- plied to the cpu (remains at "h") until timer 2 underflows. this al- lows time for the clock circuit oscillation to stabilize. the internal clock f is supplied for the first time, when timer 2 underflows. therefore make sure not to set the timer 2/int 3 interrupt request bit to "1" be- fore the stp instruction stops the oscillator. when the ______ oscillator is restarted by reset apply "l" level to port reset until the oscillation is stable since a wait time will not be generated. (2) wait mode if the wit instruction is executed, the internal clock f stops at an "h" level. the states of x in and x cin are the same as the state before executing the wit instruction. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, nor- mal operation can be started immediately after the clock is restarted. clock generating circuit the 3807 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer's recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after poweron, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. l frequency control (1) middle-speed mode the internal clock f is the frequency of x in divided by 8. after reset, this mode is selected. (2) high-speed mode the internal clock f is half the frequency of x in . (3) low-speed mode the internal clock f is half the frequency of x cin . n note if you switch the mode between middle/high-speed and low-speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately after poweron and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(x in ) > 3f(x cin ). (4) low power consumption mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to "1." when the main clock x in is re- started (by setting the main clock stop bit to "0"), set enough time for oscillation to stabilize. by clearing furthermore the x cout drivability selection bit (b3) of cpu mode register to "0", low power consumption operation of less than 55 m a (v cc =3 v, x cin =32 khz) can be realized by reducing the drivability between x cin and x cout . at reset or during stp instruc- tion execution this bit is set to "1" and a reduced drivability that has an easy oscillation start is set. the sub-clock x cin -x cout oscillating circuit can not directly input clocks that are generated externally. ac- cordingly, make sure to cause an external resonator to oscillate. l oscillation control (1) stop mode if the stp instruction is executed, the internal clock f stops at an "h" level, and x in and x cin oscillators stop. timer 1 is set to "ff 16 " and timer 2 is set to "01 16 ." either x in or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 123 mode register except timer 3 count source selection bit (b4) are cleared to "0". set the timer 2/int 3 interrupt source bit to "1" and timer 1/int 2 as well as timer 2/int 3 interrupt enable bit to disabled x cin x cout x in x out c in c out c cin c cout rf rd x in x out external oscillation circuit v cc v ss open c cin c cout rf rd x cin x cout fig. 56. external clock input circuit fig. 55. ceramic resonator circuit 51 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer fig. 57. system clock generating circuit block diagram (single-chip mode) wit instruction stp instruction timing f (internal clock) s r q stp instruction s r q main clock stop bit s r q 1/2 1/4 x in x out x cout x cin interrupt request reset interrupt disable flag l 1/2 port x c switch bit "1" "0" "10" "01" timer 1 count source selection bits low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note) note: either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of cpu mode register. when low-speed mode is selected, set port xc switch bit (b4) to ?? "1" "0" timer 1 timer 2 timer 2 count source selection bit "00" main clock division ratio selection bits (note) 52 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer cm 4 : port xc switch bit 0 : i/o port function (stop oscillating) 1 : x cin -x cout oscillating function cm 5 : = main clock (x in - x out ) stop bit 0 : operating 1 : stopped cm 7 ,cm 6 : main clock division ratio selection bit b7 b6 0 0 : f(x in )/2 ( high-speed mode) 0 1 : f(x in )/8 (middle-speed mode) 1 0 : f(x cin )/2 (low-speed mode) 1 1 : not available note reset cm 4 "1 " "0 " cm 4 "0 " "1 " cm 6 "1 " "0 " cm 4 "1 " "0 " cm 6 "1 " "0 " cm 7 "1 " "0 " cm 4 "1 " "0 " cm 5 "1 " "0 " cm 6 "1 " "0 " cm 6 "1 " "0 " cpu mode register (cpum : address 003b 16 ) b7 b4 cm 7 "0 " "1 " cm 6 "1 " "0 " cm 7 =0 cm 6 =1 cm 5 =0(8mhz oscillating) cm 4 =0(32khz stopped) 1:switch the mode by the allows shown between the mode blocks. (do not switch between the mode directly without an allow . ) 2:the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3:timer operates in the wait mode. 4:when the stop mode is ended, a delay of approximately 1 ms occurs by timer 1 and timer 2 in middle/high-speen mode. 5:when the stop mode is ended, a delay of approximately 0.25 s occurs by timer 1 and timer 2 in low-speed mode. 6:wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle/high- speed mode. 7:the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal clock. middle-speed mode (f( ) =1 mhz) cm 7 =0 cm 6 =1 cm 5 =0(8mhz oscillating) cm 4 =1(32khz oscillating) middle-speed mode (f( ) =1mhz) cm 7 =0 cm 6 =0 cm 5 =0(8mhz oscillating) cm 4 =0(32khz stopped) high-speed mode (f( ) =4mhz) cm 7 =0 cm 6 =0 cm 5 =0(8mhz oscillating) cm 4 =1(32khz oscillating) high-speed mode (f( ) =4mhz) cm 7 =1 cm 6 =0 cm 5 =0(8mhz oscillating) cm 4 =1(32khz oscillating) low-speed mode (f( ) =16 khz) cm 7 =1 cm 6 =0 cm 5 =1(8mhz stopped) cm 4 =1(32khz oscillating) low-speed mode (f( ) =16 khz) fig. 58. state transitions of system clock = = 53 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer processor mode single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits (cm 0 and cm 1 : b1 and b0 of address 003b 16 ). in memory expansion mode and microprocessor mode, memory can be ex- panded externally through ports p0 to p3. in these modes, ports p0 to p3 lose their i/o port functions and become bus pins. table. 7. port functions in memory expansion mode and microprocessor mode port name function port p0 outputs 8-bits low-order byte of address. port p1 outputs 8-bits high-order byte of address. port p2 operates as i/o pins for data d 7 to d 0 (including instruction code) port p3 p3 0 and p3 1 function only as output pins (except that the port latch cannot be read). ____ p3 2 is the onw input pin. p3 3 is the rest out output pin. ( note ) p3 4 is the f output pin. p3 5 is the sync output pin. ___ ___ p3 6 is the wr output pin, and p3 7 is the rd output pin. note : if cnv ss is connected to v ss , the microcomputer goes to single-chip mode after a reset, so this pin cannot be used as the reset out output pin. (1) single-chip mode select this mode by resetting the microcomputer with cnv ss connected to v ss . (2) memory expansion mode select this mode by setting the processor mode bits (b1, b0) to "01" in software with cnv ss connected to v ss . this mode enables external memory expansion while maintaining the validity of the internal rom. however, some i/o devices will not support the memory expansion mode. internal rom will take precedence over external memory if addresses conflict. (3) microprocessor mode select this mode by resetting the microcomputer with cnv ss con- nected to v cc , or by setting the processor mode bits to "10" in soft- ware with cnv ss connected to v ss . in microprocessor mode, the internal rom is no longer valid and external memory must be used. fig. 59. memory maps in various processor modes fig. 60. structure of cpu mode register 0000 16 0040 16 0840 16 0008 16 0000 16 0840 16 yyyy 16 ffff 16 0008 16 0040 16 ffff 16 internal ram reserved area internal rom memory expansion mode the shaded area are external memory area. sfr area yyyy 16 indicates the first address of internal rom. sfr area microprocessor mode * *: internal ram reserved area b0 cpu mode register (cpum : address 003b 16 ) processor mode bits (cm 1 , cm 0 ) b1 b0 0 0: single-chip mode 0 1: memory expansion mode 1 0: microprocessor mode 1 1: not available stack page selection bit 0: 0 page 1: 1 page b7 54 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer bus control at memory expansion _____ the 3807 group has a built-in onw function to facilitate access to external (expanded) memory and i/o devices in memory expansion mode or microprocessor mode. _____ if an "l" level signal is input to port p3 2 /onw when the cpu is in a read or write state, the corresponding read or write cycle is extended ___ ___ by one cycle of f . during this extended period, the rd or wr signal remains at "l". this extension function is valid only for writing to and reading from addresses 0000 16 to 0007 16 and 0840 16 to ffff 16 , and only read and write cycles are extended. _____ fig. 61. onw function timing f rd wr onw * * read cycle write cycle dummy cycle write cycle read cycle dummy cycle ad 15 ad 0 * period during which onw input signal is received during this period, the onw signal must be fixed at either "h" or "l". at all other times, the input level of the onw signal has no affect on operations. the bus cycles is not extended for an address in the area 0008 16 to 083f 16, regardless of whether the onw signal is received. * 55 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is "1." after a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immediately after they have been written. after writing to an interrupt request reg- ister, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations ?to calculate in decimal notation, set the decimal mode flag (d) to "1", then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after executing an adc or sbc instruction, execute at least one instruction before ex- ecuting a sec, clc, or cld instruction. ?in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ?the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. ?the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ?the data transfer instruction (lda, etc.) ?the operation instruction when the index x mode flag (t) is "1" ?the addressing mode which uses the value of a direction register as an index ?the bit-test instruction (bbc or bbs, etc.) to a direction register ?the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direction registers. serial i/o in clock synchronous serial i/o, if the receive side is using an external clock and it is to output the s rdy1 signal, set the transmit enable bit, the receive enable bit, and the s rdy1 output enable bit to "1." serial i/o1 continues to output the final bit from the t x d pin after transmission is completed. s out2 pin for serial i/o2 goes to high im- pedance after transfer is completed. when in serial i/o1 (clock-synchronous mode) or in serial i/o2 an external clock is used as synchronous clock, write transmission data to both the transmit buffer register and serial i/o2 register, during transfer clock is h. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d _____ conversion. (when the onw pin has been set to "l", the a-d conver- sion will take twice as long to match the longer bus cycle, and so f(x in ) must be at least 1 mhz.) do not execute the stp or wit instruction during an a-d conver- sion. d-a converter the accuracy of the d-a converter becomes rapidly poor under the v cc = 4.0 v or less condition; a supply voltage of v cc 3 4.0 v is recommended. when a d-a converter is not used, set all values of d-ai conversion registers (i=1 to 4) to "00 16 ." instruction execution time the instruction execution time is obtained by multiplying the frequency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency in high-speed mode. _____ when the onw function is used in modes other than single-chip mode, the frequency of the internal clock f may be one fourth of the x in frequency. 56 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer notes on usage handling of source pins in order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (v cc pin ) and gnd pin (vss pin) and between power source pin (v cc pin ) and analog power source input pin (av ss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 m f0.1 m f is recommended. p3 4 clock output function in the case of using an i/o port p3 4 as a clock output function, note the following : when an output clock frequency is changed during outputting a clock, the port may feed a noise having a shorter pulse width than the standard at the switch timing. besides, it also may happen at the timing for switching the low-speed mode to the middle/ high-speed mode. timer x and timer y in the pulse period measurement mode or the pulse width measure- ment mode for timers x and y, set the "l" or "h" pulse width of input signal from cntr 0 /cntr 1 pin to 2 cycles or more of a timer count source. eprom version/one time prom version the cnv ss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnv ss pin and v ss pin or v cc pin with 1 to 10 k w resistance. the mask rom version track of port cnv ss has no operational inter- ference even if it is connected via a resistor. 57 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical cop- ies) rom programming method the built-in prom of the blank one time prom version and built-in eprom version can be read or programmed with a general purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. table. 8. special programming adapter package name of programming adapter 80p6n-a pca4738f-80a 80d0 pca4738l-80a the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 64 is recommended to verify programming. fig. 62. programming and testing of one time prom version programming with prom programmer screening (caution) (150? for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 ? exceeding 100 hours. caution : 58 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer electrical characteristics table 9 absolute maximum ratings absolute maximum ratings conditions symbol ratings unit parameter v cc cmpv cc v i v i v i v i v i v id v o v o p d t opr t stg power source voltage analog comparator power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 5 , p7 0 Cp7 7 , p8 0 Cp8 7 , adv ref input voltage ____________ reset, x in input voltage cnv ss (rom version) input voltage cnv ss (prom version) in-phase input voltage cmp in , cmp ref differential input voltage |cmp in Ccmp ref | output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , p7 0 Cp7 7 , p8 0 Cp8 7 , x out output voltage cmp out power dissipation operating temperature storage temperature C0.3 to 7.0 C0.3 to 7.0 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to 7 C0.3 to 13 C0.3 to cmpv cc +0.3 cmpv cc C0.3 to v cc +0.3 C0.3 to cmpv cc +0.3 500 C20 to 85 C40 to 125 v v v v v v v v v v mw c c ta = 25 c all voltages are based on v ss . output transistors are cut off. 59 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer table 10 recommended operating conditions (1) (vcc = 2.7 to 5.5 v, ta = C 20 to 85 c, unless otherwise noted) recommended operating conditions v v v v v v v v v v v v v v v v v 5.5 5.5 v cc v cc v cc v cc v cc v cc v cc 0.2v cc 0.2v cc 0.8 0.2v cc 0.16v cc 2.7 4.0 2.0 2.7 av ss 0.8v cc 0.8v cc 2.0 0.8v cc 0 0 0 0 0 min. typ. max. symbol parameter unit v cc v ss adv ref dav ref cmpv cc av ss v ia v ih v ih v ih v ih v il v il v il v il v il power source voltage power source voltage a-d comparator reference voltage d-a comparator reference voltage analog comparator power source voltage analog power source voltage a-d comparator input voltage an 0 an 12 h input voltage p0 0 p0 7 , p1 0 p1 7 , p3 0 , p3 1 , p3 3 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 5 , p7 0 p7 7 , p8 0 p8 7 h input voltage (cmos input level selected) p2 0 p2 7 , p3 2 h input voltage (ttl input level selected) p2 0 p2 7 , p3 2 (note) h input voltage ______ reset, x in , cnv ss l input voltage p0 0 p0 7 , p1 0 p1 7 , p3 0 , p3 1 , p3 3 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 5 , p7 0 p7 7 , p8 0 p8 7 l input voltage (cmos input level selected) p2 0 p2 7 , p3 2 l input voltage (ttl input level selected) p2 0 p2 7 , p3 2 (note) l input voltage ______ reset, cnv ss l input voltage x in f(x in ) 4.1mhz f(x in ) = 8mhz 5.0 5.0 0 v cc 0 limits note: when vcc is 4.0 to 5.5 v. h total peak output current (note) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 h total peak output current (note) p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , cmp out , p7 0 Cp7 7 l total peak output current (note) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p8 0 Cp8 7 l total peak output current (note) p2 4 Cp2 7 l total peak output current (note) p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , cmp out , p7 0 Cp7 7 h total average output current (note) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 h total average output current (note) p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , cmp out , p7 0 Cp7 7 l total average output current (note) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p8 0 Cp8 7 l total average output current (note) p2 4 Cp2 7 l total average output current (note) p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , cmp out , p7 0 Cp7 7 min. typ. max. symbol parameter limits unit ? i oh(peak) ? i oh(peak) ? i ol(peak) ? i ol(peak) ? i ol(peak) ? i oh(avg) ? i oh(avg) ? i ol(avg) ? i ol(avg) ? i ol(avg) in single chip mode in memory expansion mode and microprocessor mode C80 C80 80 80 80 80 C40 C40 40 40 40 40 ma ma ma ma ma ma ma ma ma ma ma ma in single chip mode in memory expansion mode and microprocessor mode table 11 recommended operating conditions (2) (vcc = 2.7 to 5.5 v, ta = C 20 to 85 c, unless otherwise noted) note: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100ms. the total peak current is the peak value of all the currents. 60 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer table 12 recommended operating conditions (3) (vcc = 2.7 to 5.5 v, ta = C 20 to 85 c, unless otherwise noted) h peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , cmp out , p7 0 Cp7 7 , p8 0 Cp8 7 l peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , cmp out , p7 0 Cp7 7 , p8 0 Cp8 7 l peak output current (note 1) p2 4 Cp2 7 h average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , cmp out , p7 0 Cp7 7 , p8 0 Cp8 7 l average output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , cmp out , p7 0 Cp7 7 , p8 0 Cp8 7 l average output current (note 2) p2 4 Cp2 7 main clock input oscillation frequency (note 3) symbol parameter limits unit i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) f(x cin ) in single chip mode in memory expansion mode and microprocessor mode 32.768 ma ma ma ma ma ma ma ma mhz mhz mhz mhz mhz khz C10 10 20 10 C5 5 15 5 8 3v cc C4 8 8 3v cc C4 50 32.768 sub-clock input oscillation frequency (note 3, 4) in single chip mode in memory expansion mode and microprocessor mode high-speed mode 4.0v v cc 5.5v high-speed mode 2.7v v cc 4.0v middle-speed mode 4.0v v cc 5.5v middle-speed mode (note 5) 2.7v v cc 4.0v middle-speed mode (note 5) 2.7v v cc 4.0v max. typ. min. note1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100ms. 3: when the oscillation frequency has a duty cyde of 50%. 4: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) f(x in )/ 3. 5: when using the timer x/y, timer a/b (real time output port), timer 1/2/3, serial i/o1, serial i/o2, and a-d converter, set the main clock input oscillation frequency to the max. 3 vccC4 (mhz). 61 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer electrical characteristics v v v v v v v m a m a m a m a m a m a ma v 2.0 0.4 5.0 5.0 C5.0 C5.0 5.5 min. typ. max. symbol parameter limits unit h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , p7 0 Cp7 7 , p8 0 Cp8 7 , cmp out (note 1) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 2 , p6 5 , p7 0 Cp7 7 , p8 0 Cp8 7 , cmp out hysteresis p4 2 , p4 3 , p5 1 Cp5 5 , p7 3 (note 2), cntr 0 , cntr 1 , int 0 Cint 4 , adt hysteresis r x d, s clk1 , s in2 , s clk2 hysteresis ____________ reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 5 , p7 0 Cp7 7 , p8 0 Cp8 7 h input current ____________ reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 5 , p7 0 Cp7 7 , p8 0 Cp8 7 l input current ____________ reset, cnv ss l input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 ram hold voltage v oh v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i ih i ih i il i il i il i il v ram i oh = C10ma v cc = 4.0 to 5.5v i oh = C1.0ma v cc = 2.7 to 5.5v i ol = 10ma v cc = 4.0 to 5.5v i ol = 1.6ma v cc = 2.7 to 5.5v v i = v cc (pin floating. pull-up transistors off) v i = v cc v i = v cc v i = v ss (pin floating. pull-up transistors off) v i = v ss v i = v ss pull-up transistors on v i = v ss when clock stopped test conditions 0.4 0.5 0.5 4 C4 C0.2 v cc C2.0 v cc C1.0 2.0 note1: p4 5 is measured when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. p7 1 , and p1 2 are measured when the p7 1 /s out2 and p7 2 /s clk2 p-channel output disable bit of the serial i/o2 control register 1 (bit 7 of address 001d 16 ). 2: p7 3 is measured when the ad external trigger valid bit of the aCd control register (bit 6 of address 0034 16 ) is 1. table 13 electrical characteristics (1) (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted ) 62 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer min. typ. max. symbol parameter limits unit test conditions i cc high-speed mode f(x in ) = 8mhz f(x cin ) = 32.768khz output transistors off high-speed mode f(x in ) = 8mhz (in wit state) f(x cin ) = 32.768khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768khz low-power dissipation mode (cm 3 = 0) output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768khz (in wit state) low-power dissipation mode (cm 3 = 0) output transistors off low-speed mode (v cc = 3v) f(x in ) = stopped f(x cin ) = 32.768khz low-power dissipation mode (cm 3 = 0) output transistors off low-speed mode (v cc = 3v) f(x in ) = stopped f(x cin ) = 32.768khz (in wit state) low-power dissipation mode (cm 3 = 0) output transistors off middle-speed mode f(x in ) = 8mhz f(x cin ) = stopped output transistors off middle-speed mode f(x in ) = 8mhz (in wit state) f(x cin ) = stopped output transistors off increment when a-d conversion is executed f(x in ) = 8mhz all oscillation stopped (in stp state) output transistors off power source current cmpi cc analog comparator power source current ta = 25 c ta = 85 c 6.8 1.6 60 20 20 5.0 4.0 1.5 800 0.1 200 13 200 40 55 10.0 7.0 1.0 10 500 ma ma m a m a m a m a ma ma m a m a m a m a table 14 electrical characteristics (2) (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) 63 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer mv m a m a v ns 3 60 cmpv cc = 5.0v cmp ref = 2.5v, rs = 0 w cmpv cc = 5.0v cmp ref = 2.5v min. typ. max. symbol parameter limits unit test conditions t conv r ladder i advref i i(ad) resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current v cc = adv ref = 5.0v adv ref = 5.0v adv ref on adv ref off 12 50 35 150 8 2 50 100 200 5 5.0 bits lsb tc( f ) k w m a m a m a min. typ. max. symbol parameter limits unit test conditions t su r o i davref resolution absolute accuracy setting time output resistor reference power source input current (note) v cc = 4.0 to 5.5v v cc = 2.7 to 4.0v 8 1.0 2.5 3 4 3.2 bits % % m s k w ma 1 2.5 note: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being 00 16 . min. typ. max. symbol parameter limits unit test conditions v io i b i io v icm a v t pd input offset voltage input bias current input offset current in-phase input voltage range voltage gain response time 1.2 50 5 5 cmpv cc C0.5 2500 table 15 a-d converter characteristics (vcc = 2.7 to 5.5 v, vss = avss = 0 v, adv ref = 2.0 v to vcc, ta = C 20 to 85 c, unless otherwise noted) table 16 d-a converter characteristics (vcc = 2.7 to 5.5 v, vss = avss = 0 v, dav ref = 2.7 v to vcc, ta = C 20 to 85 c, unless otherwise noted) table 17 analog comparator characteristics (vcc = 2.7 to 5.5 v, vss = avss = 0 v, cmpvcc = 2.7 v to vcc, ta = C 20 to 85 c, unless otherwise noted) a-d converter characteristics d-a converter characteristics analog comparator characteristics 64 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer timing requirements table 18 timing requirements (1) (vcc = 4.0 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) min. typ. max. symbol parameter limits unit ____________ t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x dCs clk1 ) t h (s clk1 Cr x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 Cs clk2 ) t h (s clk2 Cs in2 ) 2 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input h pulse width int 0 to int 4 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 clock input set up time serial i/o1 clock input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input set up time serial i/o2 clock input hold time note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). max. symbol parameter unit min. typ. ____________ t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x dCs clk1 ) t h (s clk1 Cr x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 Cs clk2 ) t h (s clk2 Cs in2 ) 2 243 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input h pulse width int 0 to int 4 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 clock input set up time serial i/o1 clock input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input set up time serial i/o2 clock input hold time note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). table 19 timing requirements (2) (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) limits 65 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer switching characteristics min. typ. max. symbol parameter limits unit ns ns ns ns ns ns ns ns ns ns ns ns ns t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 Ct x d) t v (s clk1 Ct x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 Cs out2 ) t v (s clk2 Cs out2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) 140 30 30 200 30 30 30 10 10 t c (s clk1 )/2C30 t c (s clk1 )/2C30 C30 t c (s clk2 )/2C160 t c (s clk2 )/2C160 0 test conditions fig. 3.1.1 fig. 3.1.1 fig. 3.1.1 note 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: when the p7 1 /s out2 , p7 2 /s clk2 p-channel output disable bit of the serial i/o2 control register1 (bit 7 of address 001d 16 ) is 0. 3: x out pin is excluded. table 20 switching characteristics (1) (vcc = 4.0 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) min. typ. max. symbol parameter limits unit test conditions t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 Ct x d) t v (s clk1 Ct x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 Cs out2 ) t v (s clk2 Cs out2 ) t f (s clk2 ) t r (cmos) t f (cmos) fig. 3.1.1 fig. 3.1.1 fig. 3.1.1 t c (s clk1 )/2C50 t c (s clk1 )/2C50 C30 t c (s clk2 )/2C240 t c (s clk2 )/2C240 0 20 20 350 50 50 400 50 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns note 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: when the p7 1 /s out2 , p7 2 /s clk2 p-channel output disable bit of the serial i/o2 control register1 (bit 7 of address 001d 16 ) is 0. 3: x out pin is excluded. table 21 switching characteristics (2) (vcc = 2.7 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) 66 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns f clock cycle time f clock h pulse width f clock l pulse width ad 15 Cad 8 delay time ad 7 Cad 0 delay time ad 15 Cad 8 valid time ad 7 Cad 0 valid time sync delay time sync valid time data bus delay time data bus valid time __ ___ rd pulse width, wr pulse width __ ___ rd pulse width, wr pulse width (when one-wait is valid) ad 15 Cad 8 delay time ad 7 Cad 0 delay time ad 15 Cad 8 valid time ad 7 Cad 0 valid time data bus delay time data bus valid time _______________ reset out output delay time _______________ reset out output valid time (note) min. symbol limits test conditions t c( f ) t wh ( f ) t wl ( f ) t d( f Cah) t d( f Cal) t v( f Cah) t v( f Cal) t d( f Csync) t v( f Csync) t d( f Cdb) t v( f Cdb) __ __ t wl (rd) , t wl (wr) __ __ t d(ahCrd) , t d(ahCwr) __ __ t d(alCrd) , t d(alCwr) __ __ t v(rdCah) , t v(wrCah) __ __ t v(rdCal) , t v(wrCal) __ t d(wrCdb) __ t v(wrCdb) _____ ____________ t d(resetCreset out ) ____________ t v( f Creset out ) typ. max. 2t c (x in ) 16 20 5 5 16 5 15 t c (x in )C16 t c (x in )C20 5 5 15 t c (x in )C10 t c (x in )C10 2 2 10 t c (x in )C10 3t c (x in )C10 t c (x in )C35 t c (x in )C40 2 2 10 0 35 40 30 30 200 100 note: the reset out output goes h in sync with the fall of the f clock that is anywhere between about 8 cycle and 13 cycles after the ____________ reset input goes h. parameter fig. 3.1.1 timing requirements in memory expansion mode and microprocessor mode switching characteristics in memory expansion mode and microprocessor mode ____ t su(onwC f ) ____ t h( f Conw) t su(dbC f ) t h( f Cdb) ____ __ ____ __ t su(onwCrd), t su(onwCwr) __ ____ __ ____ t h(rdConw) , t h(wrConw) __ t su(dbCrd) __ t h(rdCdb) _________ onw input set up time _________ onw input hold time data bus set up time data bus hold time ________ onw input set up time _________ onw input hold time data bus set up time data bus hold time min. typ. max. symbol parameter limits unit C20 C20 50 0 C20 C20 50 0 ns ns ns ns ns ns ns ns table 22 timing requirements in memory expansion and microprocessor mode(1) (vcc = 4.0 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, in high-speed mode, unless otherwise noted) table 23 switching characteristics in memory expansion and microprocessor mode(1) (vcc = 4.0 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, in high-speed mode, unless otherwise noted) 67 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer measurement output pin 100pf cmos output 100pf n-channel open-drain outpu t 1k measurement output pin fig. 63 circuit for measuring output switching fig. 64 circuit for measuring output switching characteristics (2) characteristics(1) 68 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer fig. 65 timing diagram (1) (in single-chip mode) 0.2v cc t wl(int) 0.8v cc t wh(int) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.2v cc t wl(x in ) 0.8v cc t wh(x in) t c(x in ) x in 0.2v cc 0.8v cc t w(reset) reset t f t r 0.2v cc t wl(cntr) 0.8v cc t wh(cntr) t c(cntr) t d(s clk1 -t x d) ,t d(s clk2- s out2 ) t v(s clk1 -t x d), t v(s clk2- s out2 ) t c(s clk1 ), t c(s clk2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) th (s clk1- r x d), t h (s clk2- s in 2) t su(r x d - s clk1 ), t su(s in2- s clk2 ) t x d s out2 r x d s in2 s clk1 s clk2 int 0 int 4 cntr 0 , cntr 1 timing diagram 69 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer fig. 66 timing diagram (2) (in memory expansion mode and microprocessor mode) t wl( ) 0.5v cc t wh( ) t c( ) t d( - ah) t d( - al) t d( - sync) t v( - ah) t v( - al) t v( - sync) t d( - wr) t v( - wr) 0.5v cc 0.5v cc 0.5v cc 0.5v cc t su(onw - ) t h( - onw ) 0.8v cc 0.2v cc 0.8v cc 0.2v cc t su(db- ) t h( - db) 0.5v cc t d( -db) t v( -db) 0.2v cc 0.8v cc 0.5v cc t d(reset- reset out ) 0.5v cc ad 15 ad 8 ad 7 ad 0 sync rd,wr onw db 0 db 7 db 0 db 7 reset reset out t v( reset out ) (at cpu reading) (at cpu writing) timing diagram in memory expansion mode and microprocessor mode (cmos level input) timing diagram in microprocessor mode - 70 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer fig. 67 timing diagram (3) (in memory expansion mode and microprocessor mode) 0.5v cc rd,wr 0.5v cc ad 15 ad 8 t d(ah-wr) t v(wr-ah) 0.5v cc ad 7 ad 0 t d(al-wr) t v(wr-al) 0.8v cc 0.2v cc db 0 db 7 0.5v cc rd t su(db-rd) t h(rd-db) 0.5v cc db 0 db 7 0.5v cc wr t d(wr-db) t v(wr-db) t h(wr-onw) 0.8v cc 0.2v cc onw t su(onw-wr) t v(rd-ah) t d(ah-rd) t d(al- rd) t v(rd-al) t h(rd-onw) t su(onw-rd) t wl(rd) t wl(wr) (at cpu reading) timing diagram in memory expansion mode and microprocessor mode (cmos level input) (at cpu writing) 71 3807 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer fig. 68 timing diagram (4) (in memory expansion mode and microprocessor mode) t wl( ) t wh( ) t c( ) t d( - ah) t d( - al) t d( - sync) t v( - ah) t v( - al) t v( - sync) t d( - wr) t v( - wr) t su(onw - ) t h( - onw ) t su(db- ) t h( - db) t d( - db) t v( - db) t d(reset- reset out ) ad 15 ad 8 ad 7 ad 0 sync rd,wr onw db 0 db 7 db 0 db 7 reset reset out t v( - reset out ) 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.4v 0.45v 2.4v 0.45v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 0.8v cc 0.2v cc (at cpu reading) (at cpu writing) timing diagram in memory expansion mode and microprocessor mode (ttl level input) timing diagram in microprocessor mode 72 mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer fig. 69 timing diagram (5) (in memory expansion mode and microprocessor mode) rd,wr ad 15 ad 8 t d(ah-wr) t v(wr-ah) ad 7 ad 0 t d(al-wr) t v(wr-al) db 0 db 7 2.0v rd t su(db-rd) t h(rd-db) db 0 db 7 wr t d(wr-db) t v(wr-db) t h(wr-onw ) onw t su(onw-wr) t v(rd-ah) t d(ah-rd) t d(al- rd) t v(rd-al) t h(rd-onw ) t su(onw-rd) t wl(wr) 0.8v 2.0v 0.8v 2.0v 0.8v 2.4v 0.45v 2.4v 0.45v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v t wl(rd) (at cpu reading) (at cpu writing) timing diagram in memory expansion mode and microprocessor mode (ttl level input) ? 1996 mitsubishi electric corp. h-df047-a ki-9609 new publication, effective sep. 1996. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. mitsubishi microcomputers 3807 group single-chip 8-bit cmos microcomputer rev. rev. no. date 1.0 first edition 9711.30 revision description list 3807 group data sheet (1/1) revision description |
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